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Zuocheng Xing
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2020 – today
- 2022
- [j25]Zerun Li, Qinglin Wang
, Yufei Zhu
Automatic Modulation Classification for MASK, MPSK, and MQAM Signals Based on Hierarchical Self-Organizing Map. Sensors 22(17): 6449 (2022) - 2021
- [j24]Yufei Zhu
Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph. IEEE Access 9: 28377-28392 (2021) - [j23]Lirui Chen
Low latency group-sorted QR decomposition algorithm for larger-scale MIMO systems. IET Commun. 15(12): 1548-1560 (2021) - [j22]Yufei Zhu
High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes. Symmetry 13(4): 700 (2021) - [c36]Xing Hu, Yang Zhang, Li Mao, Jie Shen, Zuocheng Xing:
A Noc Centric Low Overhead Multi-chip Interconnection Technology. HPCC/DSS/SmartCity/DependSys 2021: 603-610 - 2020
- [j21]Lirui Chen
Efficient MIMO Preprocessor With Sorting-Relaxed QR Decomposition and Modified Greedy LLL Algorithm. IEEE Access 8: 54085-54099 (2020) - [j20]Yu Wang
An Area-Efficient Hybrid Polar Decoder With Pipelined Architecture. IEEE Access 8: 68068-68082 (2020) - [j19]Zerun Li, Qinglin Wang, Weisong Liu
Practical AMC model based on SAE with various optimisation methods under different noise environments. IET Commun. 14(22): 4081-4088 (2020) - [c35]Yu Wang, Shikai Qiu, Lirui Chen, Qinglin Wang, Yang Zhang, Cang Liu, Zuocheng Xing:
A Low-Latency Successive Cancellation Hybrid Decoder for Convolutional Polar Codes. ICASSP 2020: 5105-5109 - [c34]Lirui Chen, Yu Wang, Zuocheng Xing, Shikai Qiu, Qinglin Wang, Yang Zhang:
A Paralleled Greedy LLL Algorithm for 16×16 MIMO Detection. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j18]Yu Wang
An Improved Concatenation Scheme of BCH-Polar Codes With Low-Latency Decoding Architecture. IEEE Access 7: 95867-95877 (2019) - [c33]Yang Zhang, Zuocheng Xing, Yu Wang, Lirui Chen, Qinglin Wang, Yufei Zhu:
Optimization Methods for Computing System in Mobile CPS. ICBDT 2019: 300-305 - [c32]Yu Wang, Lirui Chen, Qinglin Wang, Yang Zhang, Zuocheng Xing:
Algorithm and Architecture for Path Metric Aided Bit-Flipping Decoding of Polar Codes. WCNC 2019: 1-6 - 2018
- [j17]Yang Zhang, Zuocheng Xing, Cang Liu, Chuan Tang, Qinglin Wang:
Locality based warp scheduling in GPGPUs. Future Gener. Comput. Syst. 82: 520-527 (2018) - [j16]Yang Zhang, Zuocheng Xing, Chuan Tang, Cang Liu:
Locality-protected cache allocation scheme with low overhead on GPUs. IET Comput. Digit. Tech. 12(3): 87-94 (2018) - [j15]Yang Zhang
CWLP: coordinated warp scheduling and locality-protected cache allocation on GPUs. Frontiers Inf. Technol. Electron. Eng. 19(2): 206-220 (2018) - [c31]Yu Wang
A Low Latency SCAN-Flip Polar Decoder for 5G Vehicular Communication. INTSYS 2018: 157-170 - 2017
- [j14]Lirui Chen, Cang Liu, Yu Wang, Zuocheng Xing, Yang Zhang, Jing Liu:
Low latency QRD algorithm for future communication. IEICE Electron. Express 14(22): 20170846 (2017) - [j13]Chuan Tang, Cang Liu, Luechao Yuan, Zuocheng Xing:
Approximate iteration detection with iterative refinement in massive MIMO systems. IET Commun. 11(7): 1152-1157 (2017) - [j12]Cang Liu, Zuocheng Xing, Luechao Yuan, Chuan Tang, Yang Zhang:
A Novel Architecture to Eliminate Bottlenecks in a Parallel Tiled QRD Algorithm for Future MIMO Systems. IEEE Trans. Circuits Syst. II Express Briefs 64-II(1): 26-30 (2017) - [j11]Cang Liu
Hardware Architecture Based on Parallel Tiled QRD Algorithm for Future MIMO Systems. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1714-1724 (2017) - [j10]Luechao Yuan
A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2789-2802 (2017) - 2016
- [j9]Chuan Tang, Cang Liu, Luechao Yuan, Zuocheng Xing:
High Precision Low Complexity Matrix Inversion Based on Newton Iteration for Data Detection in the Massive MIMO. IEEE Commun. Lett. 20(3): 490-493 (2016) - [j8]Cang Liu, Chuan Tang, Luechao Yuan, Zuocheng Xing, Yang Zhang:
QR decomposition architecture using the iteration look-ahead modified Gram-Schmidt algorithm. IET Circuits Devices Syst. 10(5): 402-409 (2016) - [c30]Suncheng Xiang, Minxuan Zhang, Zuocheng Xing, Cang Liu:
Hardware design of ML algorithm in MIMO-OFDM system. ICSAI 2016: 965-970 - [c29]Yang Zhang, Zuocheng Xing, Cang Liu, Chuan Tang, Lirui Chen, Qinglin Wang:
Optimization of Two Bottleneck Programs in SAR System on GPGPU. NCCET 2016: 115-124 - [c28]Yang Zhang, Zuocheng Xing, Li Zhou, Chunsheng Zhu:
Locality Protected Dynamic Cache Allocation Scheme on GPUs. Trustcom/BigDataSE/ISPA 2016: 1524-1530 - [c27]Cang Liu, Chuan Tang, Zuocheng Xing, Lirui Chen, Yang Zhang, Guitao Fu:
An Architecture of Parallel Tiled QRD Algorithm for MIMO-OFDM Systems. Trustcom/BigDataSE/ISPA 2016: 2092-2096 - [c26]Cang Liu, Chuan Tang, Zuocheng Xing, Luechao Yuan, Yu Wang, Lirui Chen, Yang Zhang, Suncheng Xiang, Wangfeng Zhao, Xing Hu, Jinsong Xu:
QRD Architecture Using the Modified ILMGS Algorithm for MIMO Systems. WICON 2016: 164-178 - 2015
- [j7]Feng Wang, Xiantuo Tang, Zuocheng Xing:
Applying Partial Power-Gating to Direction-Sliced Network-on-Chip. J. Electr. Comput. Eng. 2015: 862387:1-862387:16 (2015) - [j6]Feng Wang, Xiantuo Tang, Zuocheng Xing:
Applying partial power-gating to bit-sliced network-on-chip. Microelectron. J. 46(11): 1002-1011 (2015) - [c25]Feng Wang, Xiantuo Tang, Zuocheng Xing, Hengzhu Liu:
UniMESH: The light-weight unidirectional channel Network-on-Chip in 2D mesh topology. CONIELECOMP 2015: 104-109 - [c24]Luechao Yuan, Gaojiang Wang, Gerd Ascheid, Cang Liu, Zuocheng Xing:
A flexible low-complexity robust THP approach for MISO downlinks with imperfect CSI. ICCC 2015: 1-5 - [c23]Yang Zhang, Zuocheng Xing, Xiao Ma:
DIPP - An LLC Replacement Policy for On-chip Dynamic Heterogeneous Multi-core Architecture. ICYCSEE 2015: 386-397 - [c22]Chuan Tang, Dan Liu, Zuocheng Xing, Peng Yang, Zhe Wang, Jiang Xu:
Memory Access Analysis of Many-core System with Abundant Bandwidth. MCSoC 2015: 187-194 - [c21]Qinglin Wang, Jie Liu, Chunye Gong, Yang Zhang, Zuocheng Xing:
A GPU-based Fast Solution for Riesz Space Fractional Reaction-Diffusion Equation. NBiS 2015: 317-323 - [c20]Chuan Tang, Cang Liu, Luechao Yuan, Zuocheng Xing:
Channel Estimation in Massive MIMO: Algorithm and Hardware. NCCET 2015: 69-84 - [c19]Cang Liu, Luechao Yuan, Zuocheng Xing, Xiantuo Tang, Guitao Fu:
A ML-Based High-Accuracy Estimation of Sampling and Carrier Frequency Offsets for OFDM Systems. NCCET 2015: 85-93 - [c18]Qinglin Wang, Jie Liu, Xiantao Cui, Guitao Fu, Chunye Gong, Zuocheng Xing:
Accelerating FDTD simulation of microwave pulse coupling into narrow slots on the Intel MIC architecture. PACRIM 2015: 263-268 - 2014
- [c17]Feng Wang, Xiantuo Tang, Qinglin Wang, Zuocheng Xing, Hengzhu Liu:
Flexible Virtual Channel Power-Gating for High-Throughput and Low-Power Network-on-Chip. DSD 2014: 504-511 - [c16]Qinglin Wang, Zuocheng Xing, Jie Liu, Xiaogang Qiang, Chunye Gong, Jiang Jiang:
Parallel 3D deterministic particle transport on Intel MIC architecture. HPCS 2014: 186-192 - [c15]Yang Zhang, Zuocheng Xing, Luechao Yuan, Cang Liu, Qinglin Wang:
The acceleration of turbo decoder on the newest GPGPU of Kepler architecture. ISCIT 2014: 199-203 - 2013
- [j5]Xiaobao Chen, Zuocheng Xing, Bingcai Sui, Shi-Ce Ni:
Reconfigurable pseudo-NMOS-like logic with hybrid MOS and single-electron transistors. IEICE Electron. Express 10(20): 20130697 (2013) - [j4]Jun Gao, Minxuan Zhang, Zuocheng Xing, Chaochao Feng:
Architecture and Implementation of a Reduced EPIC Processor. IEICE Trans. Inf. Syst. 96-D(1): 9-18 (2013) - [j3]Chaochao Feng, Zhonghai Lu
Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1053-1066 (2013) - [c14]Xiantuo Tang, Feng Wang, Zuocheng Xing, Qinglin Wang:
Backhaul-Route Pre-Configuration Mechanism for Delay Optimization in NoCs. NCCET 2013: 208-217 - [c13]Xiaobao Chen, Zuocheng Xing, Bingcai Sui:
Tunable Negative Differential Resistance of Single-Electron Transistor Controlled by Capacitance. NCCET 2013: 228-234 - [c12]Xiaobao Chen, Zuocheng Xing, Bingcai Sui:
A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature. NCCET 2013: 244-250 - [c11]Luechao Yuan, Zuocheng Xing, Yang Zhang, Xiaobao Chen:
An Optimizing Strategy Research of LDPC Decoding Based on GPGPU. TrustCom/ISPA/IUCC 2013: 1901-1906 - 2012
- [c10]Xiaobao Chen, Zuocheng Xing, Bingcai Sui:
Validation and analysis of negative differential resistance of single-electron transistor with conductance model. ICECS 2012: 813-816 - 2011
- [j2]Anguo Ma, Yu Cheng, Zuocheng Xing:
Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design. J. Comput. Sci. Technol. 26(3): 504-519 (2011) - [c9]Xiaobao Chen, Zuocheng Xing, Bingcai Sui:
A model for energy quantization of single-electron transistor below 10nm. ASICON 2011: 531-534 - [c8]Yu Cheng, Yongwen Wang, Zuocheng Xing, Minxuan Zhang:
Characterizing Time-Varying Behavior and Predictability of Cache AVF. INCoS 2011: 720-725 - [c7]Guitao Fu, Zuocheng Xing, Tianlei Zhao, Xiantuo Tang:
Design and Evaluation of Traffic Filter for Token Protocol. PARELEC 2011: 67-72 - 2010
- [c6]Shubo Qi, Jinwen Li, Zuocheng Xing, Xiaomin Jia, Minxuan Zhang:
A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network. ISVLSI 2010: 316-320
2000 – 2009
- 2009
- [j1]Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Jing Du, Ying Zhang:
Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming. IEEE Trans. Parallel Distributed Syst. 20(8): 1142-1157 (2009) - [c5]Anguo Ma, Jing Cai, Yu Cheng, Xiaoqiang Ni, Yuxing Tang, Zuocheng Xing:
Performance Optimization Strategies of High Performance Computing on GPU. APPT 2009: 150-164 - [c4]Ping Zhang, Yanmin Song, Jianmin Zhang, Zuocheng Xing:
Design of Testing Struture in Microprocessor Based on JTAG. ISCID (1) 2009: 223-226 - [c3]Jiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing:
Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture. ReConFig 2009: 48-53 - 2007
- [c2]Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Ying Zhang:
A 64-bit stream processor architecture for scientific applications. ISCA 2007: 210-219 - 2006
- [c1]Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing:
An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. Asia-Pacific Computer Systems Architecture Conference 2006: 588-594
Coauthor Index
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last updated on 2024-08-08 20:11 CEST by the dblp team
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