research-article

Crosstalk noise and bit error rate analysis for optical network-on-chip

Authors:

Qi Li,

Weichen LiuAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 657 - 660

https://doi.org/10.1145/1837274.1837441

Published: 13 June 2010 Publication History

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Abstract

Crosstalk noise is an intrinsic characteristic of photonic devices used by optical networks-on-chip (ONoCs) as well as a potential issue. For the first time, this paper analyzed and modeled the crosstalk noise, signal-to-noise ratio (SNR), and bit error rate (BER) of optical routers and ONoCs. The analytical models for crosstalk noise, minimum SNR, and maximum BER in meshbased ONoCs are presented. An automated crosstalk analyzer for optical routers is developed. We find that crosstalk noise significantly limits the scalability of ONoCs. For example, due to crosstalk noise, the maximum BER is 10^-3 on the 8x8 mesh-based ONoC using an optimized crossbar-based optical router. To achieve the BER of 10^-9 for reliable transmissions, the maximum ONoC size is 6x6. A novel compact high-SNR optical router is proposed to improve the maximum ONoC size to 8x8.

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Cited By

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Zheng ZLi MTseng TSchlichtmann U(2023)LightR: A Fault-Tolerant Wavelength-Routed Optical Networks-on-Chip TopologyApplied Sciences10.3390/app1315887113:15(8871)Online publication date: 1-Aug-2023
https://doi.org/10.3390/app13158871
Truppel ATseng TSchlichtmann U(2023)Accurate Infinite-Order Crosstalk Calculation for Optical Networks-on-ChipJournal of Lightwave Technology10.1109/JLT.2022.321015941:1(4-16)Online publication date: 1-Jan-2023
https://doi.org/10.1109/JLT.2022.3210159
Jadhav NChaudhari BKhandekar P(2023)SNR Modeling and Analysis for Two Dimensional and Three Dimensional ONoC2023 IEEE 8th International Conference for Convergence in Technology (I2CT)10.1109/I2CT57861.2023.10126293(1-5)Online publication date: 7-Apr-2023
https://doi.org/10.1109/I2CT57861.2023.10126293
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Index Terms

Crosstalk noise and bit error rate analysis for optical network-on-chip
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
2. Hardware
  1. Integrated circuits
  2. Very large scale integration design
    1. VLSI system specification and constraints

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Published In

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2010

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DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Zheng ZLi MTseng TSchlichtmann U(2023)LightR: A Fault-Tolerant Wavelength-Routed Optical Networks-on-Chip TopologyApplied Sciences10.3390/app1315887113:15(8871)Online publication date: 1-Aug-2023
https://doi.org/10.3390/app13158871
Truppel ATseng TSchlichtmann U(2023)Accurate Infinite-Order Crosstalk Calculation for Optical Networks-on-ChipJournal of Lightwave Technology10.1109/JLT.2022.321015941:1(4-16)Online publication date: 1-Jan-2023
https://doi.org/10.1109/JLT.2022.3210159
Jadhav NChaudhari BKhandekar P(2023)SNR Modeling and Analysis for Two Dimensional and Three Dimensional ONoC2023 IEEE 8th International Conference for Convergence in Technology (I2CT)10.1109/I2CT57861.2023.10126293(1-5)Online publication date: 7-Apr-2023
https://doi.org/10.1109/I2CT57861.2023.10126293
Asadi BZia SAl-Khafaji HMohamadian A(2023)Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A SurveyJournal of Electronic Testing10.1007/s10836-023-06046-x39:1(11-25)Online publication date: 28-Feb-2023
https://doi.org/10.1007/s10836-023-06046-x
Liu YZhang JFeng JChen SXu J(2022)A Reliability Concern on Photonic Neural Networks2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774661(1059-1064)Online publication date: 14-Mar-2022
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Lu YChen KHsu YChang YOshana R(2022)Thermal-aware optical-electrical routing codesign for on-chip signal communicationsProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530404(1279-1284)Online publication date: 10-Jul-2022
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Xiao MTseng TSchlichtmann U(2022)Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.315124741:12(5261-5274)Online publication date: Dec-2022
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Lu YYu SChang Y(2022)On-Chip Optical Routing With Provably Good Algorithms for Path Clustering and AssignmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313385641:11(4653-4666)Online publication date: Nov-2022
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Lu YChen YYu SChang Y(2022)Topological Structure and Physical Layout Co-Design for Wavelength-Routed Optical Networks-on-ChipIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310114541:7(2237-2249)Online publication date: Jul-2022
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