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Hans Mertens
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2020 – today
- 2024
- [c16]Hans Mertens, Frances Zhu:
Comparative Analysis of Uncertainty Quantification Models in Active Learning for Efficient System Identification of Dynamical Systems. CASE 2024: 1869-1876 - [c15]Hiroaki Arimura, Hans Mertens, Jacopo Franco, L. Lukose, W. Maqsood, S. Brus, Thomas Chiarella, A. Impagnatiello, S. Homkar, V. K. Mootheri, C. Yin, G. Alessio Verni, M. Givens, L. Petersen Barbosa Lima, S. Biesemans, N. Horiguchi:
Vt Fine-Tuning in Multi-Vt Gate-All-Around Nanosheet nFETs Using Rare-Earth Oxide-Based Dipole-First Gate Stack Compatible with CFET Integration. VLSI Technology and Circuits 2024: 1-2 - [c14]Steven Demuynck, Victor Vega-Gonzalez, C. Toledo de Carvalho Cavalcante, L. Petersen Barbosa Lima, K. Stiers, C. Sheng, A. Vandooren, M. Hosseini, X. Zhou, Hans Mertens, Thomas Chiarella, Jürgen Bömmels, Roger Loo, E. Rosseel, Clement Porret, Y. Shimura, A. Akula, G. Mannaert, S. Choudhury, V. Brissonneau, E. Dupuy, T. Sarkar, Nathali Franchina-Vergel, A. Peter, Nicolas Jourdan, J. P. Soulie, Kevin Vandersmissen, F. Sebaai, P. Puttarame Gowda, K. Lai, A. Mingardi, S. Sumar Sarkar, K. D'Have, B. T. Chan, A. Sepulveda Marquez, R. Langer, I. Gyo Koo, E. Altamirano Sanchez, Katia Devriendt, P. Rincon Delgadillo, F. Lazzarino, Jérôme Mitard, J. Geypen, E. Grieten, D. Batuk, Y.-F. Chen, F. Verbeek, F. Holsteyns, S. Subramanian, N. Horiguchi, S. Biesemans:
Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c13]Erik Bury, Michiel Vandemaele, Jacopo Franco, Adrian Chasin, Stanislav Tyaginov, A. Vandooren, Romain Ritzenthaler, Hans Mertens, Javier Diaz-Fortuny
, N. Horiguchi, Dimitri Linten, Ben Kaczer:
Reliability challenges in Forksheet Devices: (Invited Paper). IRPS 2023: 1-8 - [c12]Michiel Vandemaele, Ben Kaczer, Erik Bury, Jacopo Franco, Adrian Chasin, Alexander Makarov, Hans Mertens, Geert Hellings, Guido Groeseneken
Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations: Invited Paper. IRPS 2023: 1-10 - [c11]Hans Mertens, M. Hosseini, Thomas Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Yusuke Oniki, Andriy Hikavyy, R. Rosseel, A. Mingardi, S. Choudhury, P. Puttarame Gowda, F. Sebaai, A. Peter, Kevin Vandersmissen, J. P. Soulie, An De Keersgieter, L. Petersen Barbosa Lima, C. Cavalcante, D. Batuk, G. T. Martinez, J. Geypen, F. Seidel, K. Paulussen, P. Favia, Jürgen Bömmels, Roger Loo
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c10]Erik Bury, Adrian Vaisman Chasin, Ben Kaczer, Michiel Vandemaele, Stanislav Tyaginov, Jacopo Franco, Romain Ritzenthaler, Hans Mertens, Pieter Weckx, N. Horiguchi, Dimitri Linten:
Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets. IRPS 2022: 5 - [c9]Michiel Vandemaele, Ben Kaczer, Stanislav Tyaginov, Erik Bury, Adrian Vaisman Chasin, Jacopo Franco, Alexander Makarov, Hans Mertens, Geert Hellings, Guido Groeseneken
Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs. IRPS 2022: 6 - 2021
- [c8]Michiel Vandemaele, Ben Kaczer, Stanislav Tyaginov, Jacopo Franco, Robin Degraeve, Adrian Vaisman Chasin, Zhicheng Wu, Erik Bury, Yang Xiang, Hans Mertens, Guido Groeseneken
The properties, effect and extraction of localized defect profiles from degraded FET characteristics. IRPS 2021: 1-7
2010 – 2019
- 2019
- [c7]Eddy Simoen, Alberto Vinicius Oliveira, Anabela Veloso, Adrian Vaisman Chasin, Romain Ritzenthaler, Hans Mertens, Naoto Horiguchi, Cor Claeys:
Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors. ASICON 2019: 1-4 - [c6]Shih-Hung Chen, Dimitri Linten, Geert Hellings, Marko Simicic
CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies. IRPS 2019: 1-7 - [c5]Michiel Vandemaele, Ben Kaczer, Stanislav Tyaginov, Zlatan Stanojevic, Alexander Makarov, Adrian Vaisman Chasin, Erik Bury, Hans Mertens, Dimitri Linten, Guido Groeseneken
Full (Vg, Vd) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs. IRPS 2019: 1-7 - 2017
- [c4]Mustafa Badaroglu, Jeff Xu, John Zhu, Da Yang, Jerry Bao, Seung Chul Song, Peijie Feng, Romain Ritzenthaler, Hans Mertens, Geert Eneman, Naoto Horiguchi, Jeffrey Smith, Suman Datta
PPAC scaling enablement for 5nm mobile SoC technology. ESSDERC 2017: 240-243 - [c3]Romain Ritzenthaler, Hans Mertens, An De Keersgieter, Jérôme Mitard, Dan Mocuta, N. Horiguchi:
Isolation of nanowires made on bulk wafers by ground plane doping. ESSDERC 2017: 300-303 - 2015
- [c2]Dmitry Yakimets, Doyoung Jang, Praveen Raghavan, Geert Eneman, Hans Mertens, P. Schuddinck, Arindam Mallik, Marie Garcia Bardon, Nadine Collaert, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Kristin De Meyer:
Lateral NWFET optimization for beyond 7nm nodes. ICICDT 2015: 1-4 - [c1]Jacopo Franco, Ben Kaczer, Philippe J. Roussel, Erik Bury, Hans Mertens, Romain Ritzenthaler, Tibor Grasser
NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures. IRPS 2015: 2
Coauthor Index
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