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Masahiro Sowa
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2010 – 2019
- 2012
- [j23]Duc-Hung Le
, Katsumi Inoue, Masahiro Sowa, Cong-Kha Pham
An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(10): 1708-1717 (2012) - 2010
- [j22]Arquimedes Canedo, Ben A. Abderazek
Compiling for Reduced Bit-Width Queue Processors. J. Signal Process. Syst. 59(1): 45-55 (2010)
2000 – 2009
- 2009
- [j21]Arquimedes Canedo, Ben A. Abderazek
Design and implementation of a queue compiler. Microprocess. Microsystems 33(2): 129-138 (2009) - [j20]Arquimedes Canedo, Ben A. Abderazek
Efficient compilation for queue size constrained queue processors. Parallel Comput. 35(4): 213-225 (2009) - [j19]Arquimedes Canedo, Ben A. Abderazek
Compiler Support for Code Size Reduction Using a Queue-Based Processor. Trans. High Perform. Embed. Archit. Compil. 2: 269-285 (2009) - 2008
- [j18]Arquimedes Canedo, Ben A. Abderazek
A new code generation algorithm for 2-offset producer order queue computation model. Comput. Lang. Syst. Struct. 34(4): 184-194 (2008) - [j17]Ben A. Abderazek
The QC-2 parallel Queue processor architecture. J. Parallel Distributed Comput. 68(2): 235-245 (2008) - [j16]Md. Musfiquzzaman Akanda, Ben A. Abderazek
Dual-execution mode processor architecture. J. Supercomput. 44(2): 103-125 (2008) - [c18]Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek
Quantitative Evaluation of Common Subexpression Elimination on Queue Machines. ISPAN 2008: 25-30 - 2007
- [j15]Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa:
Optimizing Reaching Definitions Overhead in Queue Processors. J. Convergence Inf. Technol. 2(4): 36-40 (2007) - [j14]Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa:
Dual-Execution Mode Processor Architecture For Embedded Applications. J. Mobile Multimedia 3(4): 347-370 (2007) - [c17]Arquimedes Canedo, Ben A. Abderazek
An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model. EUC 2007: 196-208 - [c16]Ben A. Abderazek
Mathematical Model for Multiobjective Synthesis of NoC Architectures. ICPP Workshops 2007: 36 - [c15]Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa:
New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP. PDCAT 2007: 185-192 - [c14]Arquimedes Canedo, Ben A. Abderazek
Queue Register File Optimization Algorithm for QueueCore Processor. SBAC-PAD 2007: 169-176 - 2006
- [j13]Ta Quoc Viet, Tsutomu Yoshinaga, Ben A. Abderazek, Masahiro Sowa:
Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters. Inf. Media Technol. 1(1): 45-57 (2006) - [j12]Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa:
Design and architecture for an embedded 32-bit QueueCore. J. Embed. Comput. 2(2): 191-205 (2006) - [j11]Ben A. Abderazek
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. J. Supercomput. 38(1): 3-15 (2006) - [c13]Ben A. Abderazek
Scalable Core-Based Methodology and Synthesizable Core for Systematic Design. ICPP Workshops 2006: 345-352 - [c12]Md. Musfiquzzaman Akanda, Ben A. Abderazek
On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation. ISPA Workshops 2006: 37-46 - 2005
- [j10]Masahiro Sowa, Ben A. Abderazek
Parallel Queue Processor Architecture Based on Produced Order Computation Model. J. Supercomput. 32(3): 217-229 (2005) - [c11]Md. Musfiquzzaman Akanda, Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa:
An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture. EUC 2005: 77-86 - [c10]Ben A. Abderazek
Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core. EUC 2005: 340-349 - 2003
- [c9]Ben A. Abderazek
On the Design of a Register Queue Based Processor Architecture (FaRM-rq). ISPA 2003: 248-262 - 2002
- [c8]Kirilka Nikolova, Masahiro Sowa:
Compiler-Controlled Parallelism-Independent Scheduling Method for Cluster Computing Systems. HPCS 2002: 182-189 - [c7]Kirilka Nikolova, Sou Pei You, Masahiro Sowa:
Compiler-Controlled Parallelism-Independent Scheduling for Parallel and Distributed Systems. PARA 2002: 484-493 - [c6]Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga:
Proposal and Design of a Parallel Queue Processor Architecture (PQP). IASTED PDCS 2002: 549-554 - 2001
- [j9]Soichi Shigeta, Kentaro Shimizu, Masahiro Sowa:
Access route control by an extended key/lock scheme. Comput. Syst. Sci. Eng. 16(5): 319-325 (2001)
1990 – 1999
- 1997
- [c5]Shusuke Okamoto, Masahiro Sowa:
Intruction Fetch Mechanism for PN-Superscalar. PDPTA 1997: 1406-1410 - [c4]Mitsuaki Nakasumi, Shusuke Okamoto, Masahiro Sowa:
Program Controlled Cache Memory on Parallel Computer. PDPTA 1997: 1423-1433 - 1996
- [c3]Shusuke Okamoto, Masahiro Sowa:
Hybrid Processor Based on VLIW and PN-Superscalar. PDPTA 1996: 623-632 - 1994
- [c2]Takaya Arita, Hiromitsu Takagi, Masahiro Sowa:
V++: An Instruction-Restructurable Processor Architecture. HICSS (1) 1994: 398-408 - 1993
- [j8]Hiromitsu Takagi, Takaya Arita, Masahiro Sowa:
A static processor-scheduling algorithm resistive to dynamic fluctuation of execution timing. Syst. Comput. Jpn. 24(8): 1-10 (1993) - 1992
- [j7]Komei Kato, Takaya Arita, Masahiro Sowa:
Delayed instruction execution on a long instruction word (LIW) computer. Syst. Comput. Jpn. 23(14): 13-23 (1992) - [j6]Takaya Arita, Hiroaki Ito, Masahiro Sowa:
Performance of the PN superscalar processor as estimated by simulation. Syst. Comput. Jpn. 23(14): 24-34 (1992) - 1991
- [j5]Takaya Arita, Masahiro Sowa:
High Speed Synchronization for a Statically Scheduled Superscalar Processor. Int. J. High Speed Comput. 3(1): 77-87 (1991) - [j4]Masahiro Sowa, Takaya Arita, Tadaaki Kawamura, Hiromitsu Takagi:
Parallel execution on the function-partitioned processor with multiple instruction streams. Syst. Comput. Jpn. 22(4): 22-28 (1991)
1980 – 1989
- 1987
- [j3]Masahiro Sowa:
A Method for Speeding up Serial Processing in Dataflow Computers by Means of a Program Counter. Comput. J. 30(4): 289-294 (1987) - [j2]Masahiro Sowa, Akitoshi Kamimura:
Performance of a simulated dataflow computer DFNDR-2. Syst. Comput. Jpn. 18(6): 100-113 (1987) - 1985
- [c1]T. Smigelski, Tadao Murata, Masahiro Sowa:
A Timed Petri Net Model and Simulation of a Dataflow Computer. PNPM 1985: 56-63 - 1982
- [j1]Masahiro Sowa, Tadao Murata:
A Data Flow Computer Architecture with Program and Token Memories. IEEE Trans. Computers 31(9): 820-824 (1982)
Coauthor Index
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