Abstract
In this work, we propose a novel dual-execution modes processor, named FunctionalAssignment RegisterMachine (FaRM), which supports both Queue and Stack execution models in a single and simple processor core.
The hardware elements, instruction formats and the major hardware components of the processor are presented in sufficient detail. We also give a preliminary evaluation result of the designed processor. From our preliminary evaluation results, we found that FaRM processor achieves about 65MHz speed and can execute both Queue and Stack execution models correctly. We also found that the novel architecture is implemented without considerable additional hardware when compared with conventional architectures with similar hardware configurations.
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Akanda, M.M., Abderazek, B.A., Sowa, M. (2006). On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation. In: Min, G., Di Martino, B., Yang, L.T., Guo, M., Rünger, G. (eds) Frontiers of High Performance Computing and Networking – ISPA 2006 Workshops. ISPA 2006. Lecture Notes in Computer Science, vol 4331. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11942634_5
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DOI: https://doi.org/10.1007/11942634_5
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