Abstract
In this research work, we present a high-level prototyping of a new processor core based on Queue architecture as starting point for application-specific processor design exploration. Using modular design structure with control logic implemented as a set of communicating state machines, we show hardware emulation and optimizations results of a parallel queue proecssor architecture (QueueCore). We also show how to to fully exploit the capabilities of the designed QueueCore, while maintaining a common source base. From the evaluation results, we show that the QueueCore prototype fits on a single conventional FPGA device, thereby obviating the need to perform multi-chip partitioning which results in a loss of resource efficiency.
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Abderazek, B.A., Kawata, S., Yoshinaga, T., Sowa, M. (2005). Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core. In: Yang, L.T., Amamiya, M., Liu, Z., Guo, M., Rammig, F.J. (eds) Embedded and Ubiquitous Computing – EUC 2005. EUC 2005. Lecture Notes in Computer Science, vol 3824. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11596356_36
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DOI: https://doi.org/10.1007/11596356_36
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30807-2
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