Oct 16, 2008 · This paper proposes a novel alternative for reducing code size by using a queue-based reduced instruction set while retaining the high ...

This paper proposes a novel alternative for reducing code size by using a queue-based reduced instruction set while retaining the high parallelism ...

Oct 16, 2008 · Compiling for reduced bit-width queue processors for Journal of Signal Processing Systems by Arquimedes Canedo et al.

One promising approach for reducing code size is to employ a “dual instruction set”, where processor architectures support a normal (usually 32-bit) Instruction ...

This paper proposes a novel alternative for reducing code size by using a queue-based reduced instruction set while retaining the high parallelism ...

Arquimedes Canedo, Ben A. Abderazek , Masahiro Sowa: Compiling for Reduced Bit-Width Queue Processors. J. Signal Process. Syst. 59(1): 45-55 (2010).

This paper presents the design of a code generation algorithm implemented in the queue compiler infrastructure to achieve high code density by using a queue- ...

This modification has the purpose of reducing the bits in the instruction and thus improving the code size of compiled programs. The PQP is a 32-bit processor.

Compiling for Reduced Bit-Width Queue Processors. Article. Apr 2010. Arquimedes ... Compiler Support for Code Size Reduction Using a Queue-Based Processor.

This paper presents a technique developed to make the compiler aware of the size of the queue register file and, thus, optimize the programs to effectively ...