On the use of hard faults to generate test sets
Pages 92 - 93
Abstract
In test set embedding Built-In Self-Test (BIST) schemes a pre-computed test set is embedded into the sequence generated by a hardware module. In this work we first apply a sequence of pseudorandom patterns and then try to embed patterns for the remaining faults (i.e. "extremely hard" faults) in the sequence generated by the hardware generator.
References
[1]
Abramovici M., Breuer M., Freidman A., "Digital Systems Testing and Testable Design", Computer science Press, 1990.
[2]
Bardell P., McAnney W., Savir J., "Built-In Test for VLSI: Pseudorandom Techniques", John Wiley and Sons, 1987.
[3]
Dufaza C., Gambon G., "LFSR-based Deterministic and Pseudorandom Test Pattern Generator Structures", Proc. European Test Conference, pp. 27--34, 1991.
[4]
Stroele A., BIST Patter Generators Using Addition and Subtraction Operations", Journal of Electronic Testing: Theory and Applications, vol. 11, pp. 69--80, 1997.
[5]
Lempel M., Gupta S., Breuer A., "Test Embedding with Discrete Logarithms", IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no 5, May 1995.
[6]
Dorsch R., Wunderlich H., "Accumulator Based Deterministic BIST", International Test Conference, pp. 412--421, 1998.
[7]
H. K. Lee and D.S. Ha, "Atalanta: an Efficient ATPG for Combinational Circuits,", Technical Report, 93--12, Dep't of Electrical Eng., Virginia Polytechnic Institute and State University, Blacksburg, Virginia, 1993.
[8]
Pohlig St., Hellman M., "An Improved Algorithm for computing Logarithms over GF(p) and its cryptographic Significance", IEEE Trans. Inf. Theory, Jan 1978, pp. 106--110.
[9]
Akers Sh., "Binary Decision Diagrams", IEEE Trans. on Comp., vol. C-27, no 6, June. 1978.
[10]
Kagaris D., Tragoudas S. Majumdar A., "On the use of Counters for reproducing Deterministic Test Sets", IEEE Transactions on Computers, vol. 45, no. 12, December 1996.
[11]
Kagaris D., Tragoudas S., "On the Design of Optimal Counter-based Schemes for test set embedding", IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no.2, February 1999.
[12]
Voyiatzis I., "Test vector Embedding into Accumulator-generated sequences: A linear-time solution", IEEE Transactions on Computers, April 2005.
[13]
H. K. Lee and D. S. Ha, "HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, pp. 1048--1058, September 1996.
[14]
Brglez F., Fujiwara H., "A neutral netlist of 10 combinational benchmarks circuits and a target translator in FORTRAN", International Symposium on Circuits and Systems, 1985.
[15]
Stroele A., Mayer Fr., "Methods to reduce test application Time for Accumulator-Based Self-Test" Proceedings of the VLSI Test Symposium 1997, pp. 48--53.
Index Terms
- On the use of hard faults to generate test sets
Recommendations
Generation of mixed test sets for transition faults
Test sets that contain both broadside and skewed-load tests are important for achieving the highest possible delay fault coverage for standard-scan circuits. Both types of tests can be represented as 〈s1 v1, s2 v2〉, where s1 and s2 are states, and v1 ...
On the Use of Mutation Faults in Empirical Assessments of Test Case Prioritization Techniques
Regression testing is an important activity in the software life cycle, but it can also be very expensive. To reduce the cost of regression testing, software testers may prioritize their test cases so that those which are more important, by some measure,...
On n-detection test sets and variable n-detection test sets for transition faults
We study the effectiveness of n-detection test sets based on transition faults in detecting defects that affect the timing behavior of a circuit. We use path delay faults as surrogates for unmodeled defects, and show that the path delay fault coverage ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
October 2015
438 pages
ISBN:9781450335515
DOI:10.1145/2801948
Copyright © 2015 ACM.
© 2015 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 01 October 2015
Check for updates
Qualifiers
- Short-paper
Funding Sources
- Greek national funds
- European Union (European Social Fund - ESF)
Conference
PCI '15
Acceptance Rates
PCI '15 Paper Acceptance Rate 64 of 148 submissions, 43%;
Overall Acceptance Rate 190 of 390 submissions, 49%
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 18Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 18 Nov 2024
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in