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Damien Hardy
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Books and Theses
- 2010
- [b1]Damien Hardy:
Analyse pire cas pour processeur multi-cœurs disposant de caches partagés. University of Rennes 1, France, 2010
Journal Articles
- 2019
- [j4]Viet Anh Nguyen, Damien Hardy, Isabelle Puaut
:
Cache-conscious off-line real-time scheduling for multi-core platforms: algorithms and implementation. Real Time Syst. 55(4): 810-849 (2019) - 2015
- [j3]Damien Hardy, Isabelle Puaut:
Static probabilistic worst case execution time estimation for architectures with faulty instruction caches. Real Time Syst. 51(2): 128-152 (2015) - 2012
- [j2]Boris Grot
Optimizing Data-Center TCO with Scale-Out Processors. IEEE Micro 32(5): 52-63 (2012) - 2011
- [j1]Damien Hardy, Isabelle Puaut:
WCET analysis of instruction cache hierarchies. J. Syst. Archit. 57(7): 677-694 (2011)
Conference and Workshop Papers
- 2023
- [c21]Antoine Gicquel
SAMVA: Static Analysis for Multi-fault Attack Paths Determination. COSADE 2023: 3-22 - 2021
- [c20]Ludovic Claudepierre, Pierre-Yves Péneau, Damien Hardy, Erven Rohou:
TRAITOR: A Low-Cost Evaluation Platform for Multifault Injection. ASSS@AsiaCCS 2021: 51-56 - 2020
- [c19]Pierre-Yves Péneau, Ludovic Claudepierre, Damien Hardy, Erven Rohou
NOP-Oriented Programming: Should we Care? EuroS&P Workshops 2020: 694-703 - 2017
- [c18]Steven Derrien, Isabelle Puaut, Panayiotis Alefragis
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach. DATE 2017: 286-289 - [c17]Viet Anh Nguyen, Damien Hardy, Isabelle Puaut:
Cache-Conscious Offline Real-Time Task Scheduling for Multi-Core Processors. ECRTS 2017: 14:1-14:22 - [c16]Sébastien Martinez, Damien Hardy, Isabelle Puaut:
Quantifying WCET reduction of parallel applications by introducing slack time to limit resource contention. RTNS 2017: 188-197 - [c15]Damien Hardy, Benjamin Rouxel, Isabelle Puaut:
The Heptane Static Worst-Case Execution Time Estimation Tool. WCET 2017: 8:1-8:12 - 2016
- [c14]Damien Hardy, Isabelle Puaut, Yiannakis Sazeides:
Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults. DATE 2016: 91-96 - [c13]Syed Aftab Rashid, Geoffrey Nelissen
Cache-Persistence-Aware Response-Time Analysis for Fixed-Priority Preemptive Systems. ECRTS 2016: 262-272 - 2015
- [c12]Suzana Milutinovic
Speeding up Static Probabilistic Timing Analysis. ARCS 2015: 236-247 - 2014
- [c11]Jaume Abella
On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques. ECRTS 2014: 266-275 - 2013
- [c10]Damien Hardy, Marios Kleanthous, Isidoros Sideris, Ali G. Saidi, Emre Ozer, Yiannakis Sazeides:
An analytical framework for estimating TCO and exploring data center design space. ISPASS 2013: 54-63 - [c9]Damien Hardy, Isabelle Puaut:
Static probabilistic worst case execution time estimation for architectures with faulty instruction caches. RTNS 2013: 35-44 - 2012
- [c8]Dragomir Milojevic
Thermal characterization of cloud workloads on a power-efficient server-on-chip. ICCD 2012: 175-182 - [c7]Damien Hardy, Isidoros Sideris, Nikolas Ladas, Yiannakis Sazeides:
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults. MICRO 2012: 48-59 - 2011
- [c6]Damien Hardy, Benjamin Lesage, Isabelle Puaut:
Scalable Fixed-Point Free Instruction Cache Analysis. RTSS 2011: 204-213 - 2009
- [c5]Damien Hardy, Thomas Piquet, Isabelle Puaut:
Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches. RTSS 2009: 68-77 - [c4]Benjamin Lesage, Damien Hardy, Isabelle Puaut:
WCET Analysis of Multi-Level Set-Associative Data Caches. WCET 2009 - 2008
- [c3]Damien Hardy, Isabelle Puaut:
Predictable Code and Data Paging for Real Time Systems. ECRTS 2008: 266-275 - [c2]Damien Hardy, Isabelle Puaut:
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches. RTSS 2008: 456-466 - 2007
- [c1]Isabelle Puaut, Damien Hardy:
Predictable Paging in Real-Time Systems: A Compiler Approach. ECRTS 2007: 169-178
Informal and Other Publications
- 2008
- [i1]Damien Hardy, Isabelle Puaut:
WCET analysis of multi-level set-associative instruction caches. CoRR abs/0807.0993 (2008)
Coauthor Index
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