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IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12
Volume 12, Number 1, January 2004
- N. Ranganathan:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 1-11 (2004) - Baris Taskin, Ivan S. Kourtev:
Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 12-27 (2004) - Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
:
Timing modeling and optimization under the transmission line model. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 28-41 (2004) - Ankur Srivastava
Timing driven gate duplication. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 42-51 (2004) - R. Galli, Alexandre F. Tenca:
A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 52-66 (2004) - Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman:
Substrate coupling in digital circuits in mixed-signal smart-power systems. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 67-78 (2004) - Antonio H. Chan, Gordon W. Roberts:
A jitter characterization system using a component-invariant Vernier delay line. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 79-95 (2004) - Tajana Simunic, Stephen P. Boyd, Peter W. Glynn:
Managing power consumption in networks on chips. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 96-107 (2004) - Girish Varatkar, Radu Marculescu
On-chip traffic modeling and synthesis for MPEG-2 video applications. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 108-119 (2004) - Roman L. Lysecky, Susan Cotterell, Frank Vahid:
A fast on-chip profiler memory using a pipelined binary tree. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 120-122 (2004)
Volume 12, Number 2, February 2004
- Christian Piguet, Narayanan Vijaykrishnan:
Guest Editorial. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 129-130 (2004) - Rajeev R. Rao, Ashish Srivastava, David T. Blaauw, Dennis Sylvester:
Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 131-139 (2004) - Afshin Abdollahi, Farzan Fallah, Massoud Pedram:
Leakage current reduction in CMOS VLSI circuits by input vector control. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 140-154 (2004) - Dongwoo Lee, David T. Blaauw, Dennis Sylvester:
Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 155-166 (2004) - Nam Sung Kim, Krisztián Flautner, David T. Blaauw, Trevor N. Mudge:
Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 167-184 (2004) - Fujio Ishihara, Farhana Sheikh
Level conversion for dual-supply systems. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 185-195 (2004) - Narender Hanchate, Nagarajan Ranganathan:
LECTOR: a technique for leakage reduction in CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 196-205 (2004) - Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao:
The Chimaera reconfigurable functional unit. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 206-217 (2004) - Meng-Da Yang, An-Yeu Wu
High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 218-226 (2004)
Volume 12, Number 3, March 2004
- Christian Piguet, Narayanan Vijaykrishnan:
Guest Editorial. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 233-234 (2004) - Amaury Nève, Helmut Schettler, Thomas Ludwig, Denis Flandre
Power-delay product minimization in high-performance 64-bit carry-select adders. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 235-244 (2004) - Hai Li, Swarup Bhunia
DCG: deterministic clock-gating for low-power microprocessor design. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 245-254 (2004) - Luca Benini
Memory energy minimization by data compression: algorithms, architectures and implementation. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 255-268 (2004) - Edgar G. Daylight, David Atienza
Memory-access-aware data structure transformations for embedded software with dynamic data accesses. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 269-280 (2004) - Mahmut T. Kandemir, Ismail Kadayif, Alok N. Choudhary, Ibrahim Kolcu:
Compiler-directed scratch pad memory optimization for embedded multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 281-287 (2004) - Elias Ahmed, Jonathan Rose:
The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 288-298 (2004) - Atul Maheshwari, Wayne P. Burleson, Russell Tessier:
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 299-311 (2004) - Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, Robert Anderson, Juan Ramon Uribe:
Overview of a compiler for synthesizing MATLAB programs onto FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 312-324 (2004) - Aristides Efthymiou
A CAM with mixed serial-parallel comparison for use in low energy caches. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 325-329 (2004)
Volume 12, Number 4, April 2004
- Jeff Alan Davis:
Guest Editorial. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 337-338 (2004) - Joni Dambre
Toward the accurate prediction of placement wire length distributions in VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 339-348 (2004) - Mario R. Casu
An electromigration and thermal model of power wires for a priori high-level reliability prediction. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 349-358 (2004) - Shamik Das, Anantha P. Chandrakasan, Rafael Reif:
Calibration of Rent's rule models for three-dimensional integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 359-366 (2004) - James W. Joyner, Payman Zarkesh-Ha, James D. Meindl:
Global interconnect design in a three-dimensional system-on-a-chip. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 367-372 (2004) - Suhrid A. Wadekar, Alice C. Parker:
Interconnect-based system-level energy and power prediction to guide architecture exploration. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 373-380 (2004) - PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
On metrics for comparing interconnect estimation methods for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 381-385 (2004) - Andrey V. Mezhiba, Eby G. Friedman:
Scaling trends of on-chip power distribution noise. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 386-394 (2004) - Seongkyun Shin, Yungseon Eo, William R. Eisenstadt
Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 395-407 (2004) - Iouliia Skliarova
A software/reconfigurable hardware SAT solver. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 408-419 (2004) - Khaled Benkrid, Danny Crookes:
From application descriptions to hardware in seconds: a logic-based approach to bridging the gap. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 420-436 (2004) - Shizhong Mei, Yehea I. Ismail:
Modeling skin and proximity effects with reduced realizable RL circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 437-447 (2004)
Volume 12, Number 5, May 2004
- Pingshan Wang, G. Pei, E. C.-C. Kan:
Pulsed wave interconnect. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 453-463 (2004) - Himanshu Kaul, Dennis Sylvester:
Low-power on-chip communication based on transition-aware global signaling (TAGS). IEEE Trans. Very Large Scale Integr. Syst. 12(5): 464-476 (2004) - Peiyi Zhao, Tarek Darwish, Magdy A. Bayoumi:
High-performance and low-power conditional discharge flip-flop. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 477-484 (2004) - Volkan Kursun
Sleep switch dual threshold Voltage domino logic with reduced standby leakage current. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 485-496 (2004) - Byonghyo Shim
Reliable low-power digital signal processing via reduced precision redundancy. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 497-510 (2004) - Nhon T. Quach, Naofumi Takagi
Systematic IEEE rounding method for high-speed floating-point multipliers. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 511-521 (2004) - Kyung-Ju Cho, Kwang-Chul Lee, Jin-Gyun Chung, Keshab K. Parhi
Design of low-error fixed-width modified booth multiplier. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 522-531 (2004)
- YongJoon Kim, Hyun-Don Kim, Sungho Kang:
A new maximal diagnosis algorithm for interconnect test. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 532-537 (2004) - Farhad H. A. Asgari, Manoj Sachdev:
A low-power reduced swing global clocking methodology. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 538-545 (2004) - Yanni Chen, Keshab K. Parhi
Small area parallel Chien search architectures for long BCH codes. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 545-549 (2004)
Volume 12, Number 6, June 2004
- Jennifer L. Wong
Power minimization in QoS sensitive systems. 553-561 - Saraju P. Mohanty, Nagarajan Ranganathan:
A framework for energy and transient power reduction during behavioral synthesis. 562-572 - Noureddine Chabini, Wayne H. Wolf:
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling. 573-589 - Weidong Wang, Anand Raghunathan
Input space adaptive design: a high-level methodology for optimizing energy and performance. 590-602 - Mahmoud Méribout
Efficient metrics and high-level synthesis for dynamically reconfigurable logic. 603-621 - Mihai Sima
Pel reconstruction on FPGA-augmented TriMedia. 622-635 - J. V. Deodhar, Spyros Tragoudas:
Implicit deductive fault simulation for complex delay fault models. 636-641 - Jun Jin Kong, Keshab K. Parhi
Low-latency architectures for high-throughput rate Viterbi decoders. 642-651 - R. Singh, N. Bhat:
An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs. 652-657 - Imed Ben Dhaou
Efficient library characterization for high-level power estimation. 657-661 - Alexandre Valentian, Olivier Thomas, Andrei Vladimirescu, Amara Amara:
Modeling subthreshold SOI logic for static timing analysis. 662-669
Volume 12, Number 7, July 2004
- Jari Nikara, Stamatis Vassiliadis, Jarmo Takala
Multiple-symbol parallel decoding for variable length codes. 676-685 - Sumio Morioka
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. 686-691 - Arif Ishaq Abou-Seido, Brian Nowak, Chris Chong-Nuen Chu:
Fitted Elmore delay: a simple and accurate interconnect delay model. 691-696 - Ivan Blunno, Luciano Lavagno:
Designing an asynchronous microcontroller using Pipefitter. 696-699 - Yongchul Song, Beomsup Kim:
Quadrature direct digital frequency synthesizers using interpolation-based angle rotation. 701-710 - Jian Liang, Andrew Laffely, Sriram Srinivasan, Russell Tessier:
An architecture and compiler for scalable on-chip communication. 711-726 - Arne Halaas, Børge Svingen, Magnar Nedland, Pål Sætrom
A recursive MISD architecture for pattern matching. 727-734 - Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho:
Placement constraints in floorplan design. 735-745 - Yi Zhao, Sujit Dey, Li Chen:
Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses. 746-755 - Sule Ozev, Alex Orailoglu:
Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead. 756-765 - Keoncheol Shin, Taewhan Kim:
Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. 766-775 - Abhijit Jas, Bahram Pouya, Nur A. Touba:
Test data compression technique for embedded cores using virtual scan chains. 775-781 - Irith Pomeranz, Sudhakar M. Reddy:
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. 780-788
Volume 12, Number 8, August 2004
- Paul Pop
Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems. 793-811 - Peter Petrov, Alex Orailoglu:
Low-power instruction bus encoding for embedded processors. 812-826 - Yen-Jen Chang, Feipei Lai, Chia-Lin Yang
Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. 827-836 - Naehyuck Chang, Inseok Choi, Hojun Shim:
DLS: dynamic backlight luminance scaling of liquid crystal display. 837-846 - Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar:
Asynchronous gate-diffusion-input (GDI) circuits. 847-856 - Tiberiu Chelcea, Steven M. Nowick:
Robust interfaces for mixed-timing systems. 857-873 - Shinn-Ying Ho, Shinn-Jang Ho, Yi-Kuang Lin, W. C.-C. Chu:
An orthogonal simulated annealing algorithm for large floorplanning problems. 874-877 - Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards:
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability. 876-880
Volume 12, Number 9, September 2004
- Rouwaida Kanj, Elyse Rosenbaum:
Critical evaluation of SOI design guidelines. 885-894 - Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Chih-Chen Li, Ron Hu:
A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula. 895-900 - Chua-Chin Wang, Yih-Long Tseng, Hon-Yuan Leo, Ron Hu:
A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches. 901-909 - Li Ding, Pinaki Mazumder:
On circuit techniques to improve noise immunity of CMOS dynamic logic. 910-925 - Sarvesh H. Kulkarni, Dennis Sylvester:
High performance level conversion for dual VDD design. 926-936 - Changbo Long, Lei He:
Distributed sleep transistor network for power reduction. 937-946 - Lawrence T. Clark, M. Morrow, W. Brown:
Reverse-body bias and supply collapse for low effective standby power. 947-956 - Xinmiao Zhang, Keshab K. Parhi
High-speed VLSI architectures for the AES algorithm. 957-967 - J. Kaza, Chaitali Chakrabarti:
Design and implementation of low-energy turbo decoders. 968-977 - Mathew A. Sacker, Andrew D. Brown, Andrew J. Rushton, Peter R. Wilson:
A behavioral synthesis system for asynchronous circuits. 978-994 - Stefania Perri
Variable precision arithmetic circuits for FPGA-based multimedia processors. 995-999
Volume 12, Number 10, October 2004
- Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska:
Individual wire-length prediction with application to timing-driven placement. 1004-1014 - Jason Helge Anderson, Farid N. Najm:
Power estimation techniques for FPGAs. 1015-1027 - Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Sequential delay budgeting with interconnect prediction. 1028-1037 - André DeHon, Raphael Rubin:
Design of FPGA interconnect for multilevel metallization. 1038-1050 - André DeHon:
Unifying mesh- and tree-based programmable interconnect. 1051-1065 - Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
Empirical models for net-length probability distribution and applications. 1066-1075 - Ketan N. Patel, Igor L. Markov:
Error-correction and crosstalk avoidance in DSM busses. 1076-1080 - Payam Heydari, Ravindran Mohanavelu:
Design of ultrahigh-speed low-voltage CMOS CML buffers and latches. 1081-1093 - Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Evaluation of energy consumption in RC ladder circuits driven by a ramp input. 1094-1107 - Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand:
Assessment of on-chip wire-length distribution models. 1108-1112 - Richard H. Turner, Roger F. Woods
Highly efficient, limited range multipliers for LUT-based FPGA architectures. 1113-1118 - Stelian Alupoaei, Srinivas Katkoori
Ant colony system application to macrocell overlap removal. 1118-1123 - Tali Moreshet, R. Iris Bahar
Effects of speculation on performance and issue queue design. 1123-1126 - Mohammad Maymandi-Nejad
Correction to "A Digitally Programmable Delay Element: Design and Analysis". 1126
Volume 12, Number 11, November 2004
- Jeong-Taek Kong:
CAD for nanometer silicon design challenges and success. 1132-1147 - Andrey V. Mezhiba, Eby G. Friedman:
Impedance characteristics of power distribution grids in nanoscale integrated circuits. 1148-1155 - Alexandre Schmid
Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors. 1156-1166 - Luigi Fortuna, Manuela La Rosa, Donata Nicolosi, Domenico Porto:
Nanoscale system dynamical behaviors: from quantum-dot-based cell to 1-D arrays. 1167-1173 - E. Y. Chou, J. C. Huang, M. S. Huang, M. C. Hsieh, A. Y. Hsu:
Baud-rate channel equalization in nanometer technologies. 1174-1181 - Jui-Lin Lai, Peter Chung-Yu Wu:
Architectural design and analysis of learnable self-feedback ratio-memory cellular nonlinear network (SRMCNN) for nanoelectronic systems. 1182-1191 - Hong-Yi Huang, Shih-Lun Chen:
Interconnect accelerating techniques for sub-100-nm gigascale systems. 1192-1200 - Garrett S. Rose
Large-signal two-terminal device model for nanoelectronic circuit analysis. 1201-1208 - Chaohong Hu, Sorin Dan Cotofana
Analog-to-digital converter based on single-electron tunneling transistors. 1209-1213 - Chris Dwyer, Leandra Vicci, John W. Poulton, Dorothy Erie
The design of DNA self-assembled computing circuitry. 1214-1220 - Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin:
Characterization and modeling of run-time techniques for leakage power reduction. 1221-1233 - Kartik Mohanram, Nur A. Touba:
Lowering power consumption in concurrent checkers via input ordering. 1234-1243 - Ramamurti Chandramouli, Vamsi K. Srikantam:
Multimode power modeling and maximum-likelihood estimation. 1244-1248 - Antonio Blotti, Roberto Saletti
Ultralow-power adiabatic circuit semi-custom design. 1248-1253 - Gerald Esch Jr., Tom Chen:
Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations. 1253-1257
Volume 12, Number 12, December 2004
- Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty
SOC test planning using virtual test access architectures. 1263-1276 - Abhijit Jas, C. V. Krishna, Nur A. Touba:
Weighted pseudorandom hybrid BIST. 1277-1283 - Miron Abramovici, Charles E. Stroud, John Marty Emmert:
Online BIST and BIST-based diagnosis of FPGA logic blocks. 1284-1294 - Magdy A. El-Moursy, Eby G. Friedman:
Power characteristics of inductive interconnect. 1295-1306 - Emad Gad
Efficient simulation of nonuniform transmission lines using integrated congruence transform. 1307-1320 - Atul Maheshwari, Wayne P. Burleson:
Differential current-sensing for on-chip interconnects. 1321-1329 - Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand:
Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models. 1330-1347 - Maged Ghoneima, Yehea I. Ismail:
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses. 1348-1359 - Sanjukta Bhanja, N. Ranganathan:
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. 1360-1370 - William N. N. Hung, Xiaoyu Song, T. Kam, Lerong Cheng, Guowu Yang:
Routability checking for three-dimensional architectures. 1371-1374 - Mauro Olivieri
Bus-switch coding for reducing power dissipation in off-chip buses. 1374-1377 - Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Ron Hu:
A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications. 1377-1381 - Myungchul Yoon:
Sequence-switch coding for low-power data transmission. 1381-1385 - Irith Pomeranz, Yervant Zorian:
Fault isolation for nonisolated blocks. 1385-1388
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