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Chunhong Chen
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2020 – today
- 2022
- [j18]Suoyue Zhan
, Chunhong Chen:
A hybrid method for signal probability and reliability estimation with combinational circuits. Integr. 87: 275-283 (2022) - [j17]Chen Zhang, Huapeng Wu, Chunhong Chen
Area-Efficient Finite Field Multiplication Using Hybrid SET-MOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4358-4366 (2022) - [c31]Chunhong Chen, Suoyue Zhan:
A Hybrid Method for Signal Probability Estimation with Combinational Circuits. APCCAS 2022: 472-475 - [c30]Suoyue Zhan, Chunhong Chen:
An Efficient Method for Sequential Circuit Reliability Estimation. MWSCAS 2022: 1-4 - [c29]Suoyue Zhan, Chunhong Chen:
Circuit Reliability Analysis with Considerations of Aging Effect. SBCCI 2022: 1-5 - 2021
- [c28]Chen Zhang, Chunhong Chen, Huapeng Wu:
Area-Efficient Finite Field Multiplication in $\text{GF} (2^{n})$ Using Single-Electron Transistors. APCCAS 2021: 25-28 - [c27]Khawja Sikander, Suoyue Zhan, Chunhong Chen:
An Analytical Model for Circuit Reliability Estimation. MWSCAS 2021: 84-87
2010 – 2019
- 2019
- [c26]Suoyue Zhan, Khawja Sikander, Chunhong Chen:
Allocating Gate Reliability for Circuit Reliability Optimization. MWSCAS 2019: 327-330 - 2018
- [c25]Chunhong Chen, Jinchen Cai, Suoyue Zhan:
A Triple-Point Model for Circuit-Level Reliability Analysis. ISCAS 2018: 1-4 - [c24]Lin Li, Chunhong Chen:
Modeling and Application for Negative-Differential-Conductance Devices with Single-Electron Technology. MWSCAS 2018: 696-699 - 2017
- [c23]Jinchen Cai, Chunhong Chen:
Circuit Reliability Analysis Using Signal Reliability Correlations. QRS Companion 2017: 171-176 - 2015
- [j16]Chunhong Chen, Ran Xiao:
A fast model for analysis and improvement of gate-level circuit reliability. Integr. 50: 107-115 (2015) - [c22]Ran Xiao, Chunhong Chen:
Power optimization design for probabilistic logic circuits. ISCAS 2015: 2593-2595 - 2014
- [j15]Ran Xiao
Gate-Level Circuit Reliability Analysis: A Survey. VLSI Design 2014: 529392:1-529392:12 (2014) - [c21]Ran Xiao, Chunhong Chen:
Implementation of the conscience mechanism using single-electron transfer in competitive learning. ISCAS 2014: 1652-1655 - 2013
- [j14]Guoqing Deng, Chunhong Chen:
Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1573-1582 (2013) - [j13]Guoqing Deng, Chunhong Chen:
A SET/MOS Hybrid Multiplier Using Frequency Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1738-1742 (2013) - [c20]Chia-Chin Liu, Chunhong Chen:
An ultra-low power voltage regulator for RFID application. MWSCAS 2013: 780-783 - 2011
- [j12]Shu-Yi Wong, Chunhong Chen:
Power efficient multi-stage CMOS rectifier design for UHF RFID tags. Integr. 44(3): 242-255 (2011) - [j11]Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu:
Low Power Chien Search for BCH Decoder Using RT-Level Power Management. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 338-341 (2011)
2000 – 2009
- 2009
- [j10]Chunni Dai, Meng Yao, Zhujie Xie, Chunhong Chen, Jingao Liu:
Parameter optimization for growth model of greenhouse crop using genetic algorithms. Appl. Soft Comput. 9(1): 13-19 (2009) - [c19]Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu:
Power-management-based Chien search for low power BCH decoder. ISLPED 2009: 299-302 - 2008
- [c18]Venketeshwaran Puthucode, Chunhong Chen:
An experimental study on multi-island structures for single-electron tunneling based threshold logic. ISCAS 2008: 600-603 - [c17]Mohammed Berhea, Chunhong Chen, Q. M. Jonathan Wu:
Protocol-level performance analysis for anti-collision protocols in RFID systems. ISCAS 2008: 1008-1011 - 2007
- [c16]Shun Li, Feng Zhou, Chunhong Chen, Hua Chen, Yipin Wu:
Quasi-Static Energy Recovery Logic with Single Power-Clock Supply. ISCAS 2007: 2124-2127 - 2006
- [j9]Chunhong Chen, Zheng Li:
A low-power CMOS analog multiplier. IEEE Trans. Circuits Syst. II Express Briefs 53-II(2): 100-104 (2006) - [c15]Yanjie Mao, Chunhong Chen:
Performance Evaluation and Optimization of Full Adders with Single-Electron Technology. CCECE 2006: 2136-2139 - [c14]Jialin Mi, Chunhong Chen, H. K. Kwan:
Power-oriented delay budgeting for combinational circuits. ISCAS 2006 - [c13]Jialin Mi, Chunhong Chen:
Finite State Machine Implementation with Single-Electron Tunneling Technology. ISVLSI 2006: 237-241 - [c12]Jialin Mi, Chunhong Chen:
Power-Oriented Delay Budgeting for Combinational Circuits. ISVLSI 2006: 361-366 - 2005
- [j8]Chunhong Chen, Jiang Zhao, Majid Ahmadi:
A Novel State Encoding Algorithm for Low Power Implementation. J. Circuits Syst. Comput. 14(3): 597-604 (2005) - 2004
- [j7]Ankur Srivastava
Timing driven gate duplication. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 42-51 (2004) - [c11]Feng Zhou, Chunhong Chen, Dawei Jin, Chenling Huang, Hao Min:
Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems. ISLPED 2004: 357-362 - 2003
- [c10]Chunhong Chen, Jiang Zhao, Majid Ahmadi:
A semi-Gray encoding algorithm for low-power state assignment. ISCAS (5) 2003: 389-392 - 2002
- [j6]Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastava
Budget Management with Applications. Algorithmica 34(3): 261-275 (2002) - [j5]Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh:
Predicting potential performance for digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3): 253-262 (2002) - [j4]Chunhong Chen, Jiang Zhao, Majid Ahmadi:
Probability-based approach to rectilinear Steiner tree problems. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 836-843 (2002) - [c9]Chunhong Chen, Majid Sarrafzadeh:
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis. DATE 2002: 1016-1020 - [c8]Chunhong Chen, Changjun Kang, Majid Sarrafzadeh:
Activity-sensitive clock tree construction for low power. ISLPED 2002: 279-282 - [c7]Chunhong Chen:
Physical design with multiple on-chip voltages. ISPD 2002: 118-118 - [c6]Chunhong Chen:
Probabilistic Analysis of Rectilinear Steiner Trees. ASP-DAC/VLSI Design 2002: 484-488 - 2001
- [j3]Amir H. Farrahi, Chunhong Chen, Ankur Srivastava
Activity-driven clock design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 705-714 (2001) - [j2]Chunhong Chen, Ankur Srivastava
On gate level power optimization using dual-supply voltages. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 616-629 (2001) - [j1]Anshuman Nayak, Malay Haldar, Prith Banerjee, Chunhong Chen, Majid Sarrafzadeh:
Power Optimization of Delay Constrained Circuits. VLSI Design 12(2): 125-138 (2001) - [c5]Ankur Srivastava, Chunhong Chen, Majid Sarrafzadeh:
Timing driven gate duplication in technology independent phase. ASP-DAC 2001: 577-582 - 2000
- [c4]Chunhong Chen, Majid Sarrafzadeh:
Power reduction by simultaneous voltage scaling and gate sizing. ASP-DAC 2000: 333-338 - [c3]Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh:
Potential Slack: An Effective Metric of Combinational Circuit Performance. ICCAD 2000: 198-201
1990 – 1999
- 1999
- [c2]Chunhong Chen, Majid Sarrafzadeh:
Provably good algorithm for low power consumption with dual supply voltages. ICCAD 1999: 76-79 - [c1]Chunhong Chen, Majid Sarrafzadeh:
An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages. ICCD 1999: 222-
Coauthor Index
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