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ACM Transactions on Reconfigurable Technology and Systems, Volume 16
Volume 16, Number 1, March 2023
- Oliver Sinnen, Qiang Liu, Azadeh Davoodi:
Introduction to Special Section on FPT'20. 1:1-1:2 - Kaichuang Shi
, Xuegong Zhou, Hao Zhou, Lingli Wang:
An Optimized GIB Routing Architecture with Bent Wires for FPGA. 2:1-2:28 - Xiang Li, Peter Stanwicks, George Provelengios, Russell Tessier, Daniel E. Holcomb:
Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud. 3:1-3:20 - Zhiqiang Que
Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. 4:1-4:26 - Niklas Schelten
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application. 5:1-5:23 - Ilias Giechaskiel
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs. 6:1-6:29 - Dennis Leander Wolf
Advantages of a Statistical Estimation Approach for Clock Frequency Estimation of Heterogeneous and Irregular CGRAs. 7:1-7:33 - Lenos Ioannou
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs. 8:1-8:26 - Xiangwei Li
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation. 9:1-9:24 - Zhuofu Tao
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator. 10:1-10:19 - Shayan Moini
Voltage Sensor Implementations for Remote Power Attacks on FPGAs. 11:1-11:21 - Amin Kalantar
FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge. 12:1-12:27 - Mário P. Véstias
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. 13:1-13:36 - Rafael Fão de Moura
Data and Computation Reuse in CNNs Using Memristor TCAMs. 14:1-14:24 - Riadh Ben Abdelhamid
A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA. 15:1-15:33 - Veronia Iskandar
Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations. 16:1-16:32
Volume 16, Number 2, June 2023
- Soheil Nazar Shahsavani
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis. 17:1-17:25 - Young Kyu Choi
FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis. 18:1-18:22 - Chanaka Ganewattha
Hardware-accelerated Real-time Drift-awareness for Robust Deep Learning on Wireless RF Data. 19:1-19:29 - Alexandre Proulx
A Survey on FPGA Cybersecurity Design Strategies. 20:1-20:33 - Stephanie Soldavini
Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics. 21:1-21:34 - Gangqiang Yang
Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain. 22:1-22:32 - Suhail Basalama
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA. 23:1-23:32 - Marius Meyer
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks. 24:1-24:27 - Tomohiro Ueno
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster. 25:1-25:32 - Ankita Nayak
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains. 26:1-26:28 - Kang Zhao
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow. 27:1-27:24 - Xingyu Tian
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs. 28:1-28:33 - Dhayalakumar M
Deterministic Approach for Range-enhanced Reconfigurable Packet Classification Engine. 29:1-29:26 - Andreas Koch, Wei Zhang:
Introduction to the Special Issue on FPT 2021. 30:1-30:2 - Sameh Attia
Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation. 31:1-31:24 - Richard Gebauer
QiCells: A Modular RFSoC-based Approach to Interface Superconducting Quantum Bits. 32:1-32:23 - Han-Sok Suh
Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA. 33:1-33:25
Volume 16, Number 3, September 2023
- Alex R. Bucknall
ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge. 34:1-34:33 - Reinout Corts
A Survey of Processing Systems for Phylogenetics and Population Genetics. 35:1-35:27 - Pedro Machado
NeuroHSMD: Neuromorphic Hybrid Spiking Motion Detector. 36:1-36:23 - Prajith Ramakrishnan Geethakumari
Stream Aggregation with Compressed Sliding Windows. 37:1-37:28 - Rasha Karakchi
NAPOLY: A Non-deterministic Automata Processor OverLaY. 38:1-38:25 - Gopal Raut
An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks. 39:1-39:32
- Miriam Leeser
Artifact Evaluation for ACM TRETS Papers Submitted from the FPT Journal Track. 40:1-40:2 - Carol Jingyi Li
Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis. 41:1-41:28 - Binglei Lou
fSEAD: A Composable FPGA-based Streaming Ensemble Anomaly Detection Library. 42:1-42:27 - Zhengyuan Shi
Design Space Exploration of Galois and Fibonacci Configuration Based on Espresso Stream Cipher. 43:1-43:24 - Gaoyu Mao
High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium. 44:1-44:28 - Pengzhou He
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography. 45:1-45:23 - HyeGang Jun
AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis. 46:1-46:30 - Liang Chang
ADAS: A High Computational Utilization Dynamic Reconfigurable Hardware Accelerator for Super Resolution. 47:1-47:22
- Christian Skubich
Increasing the Robustness of TERO-TRNGs Against Process Variation. 48:1-48:29 - Nicolai Fiege
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining. 49:1-49:32 - Aman Arora
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration. 50:1-50:34
Volume 16, Number 4, December 2023
- Jing Li
Introduction to the Special Section on FCCM 2022. 51:1-51:2 - Guiming Wu
Topgun: An ECC Accelerator for Private Set Intersection. 52:1-52:30 - Tiancheng Xu
An FPGA Accelerator for Genome Variant Calling. 53:1-53:29 - Lana Josipovic
Resource Sharing in Dataflow Circuits. 54:1-54:27 - Jianyi Cheng
Parallelising Control Flow in Dynamic-scheduling High-level Synthesis. 55:1-55:32
- Paolo Ienne
Introduction to the Special Section on FPGA 2022. 56:1-56:2 - Erwei Wang
Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks. 57:1-57:25 - Yizhao Gao
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking. 58:1-58:26 - Licheng Guo
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. 59:1-59:30
- Anouar Nechi
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing? 60:1-60:32 - Marcos T. Leipnitz
Constraint-Aware Multi-Technique Approximate High-Level Synthesis for FPGAs. 61:1-61:28 - Kenneth Liu
CHIP-KNNv2: A Configurable and High-Performance K-Nearest Neighbors Accelerator on HBM-based FPGAs. 62:1-62:26 - Licheng Guo
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. 63:1-63:31 - Yingchun Lu
High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator. 64:1-64:23
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