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Arash Fayyazi
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2020 – today
- 2024
- [c17]Seyedarmin Azizi, Mahdi Nazemi, Arash Fayyazi, Massoud Pedram:
Automated Optimization of Deep Neural Networks: Dynamic Bit-Width and Layer-Width Selection via Cluster-Based Parzen Estimation. DATE 2024: 1-6 - [c16]Arash Fayyazi
, Mahdi Nazemi
NeuroBlend: Towards Low-Power yet Accurate Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions. ACM Great Lakes Symposium on VLSI 2024: 730-735 - [c15]Mohammad Erfan Sadeghi
PEANO-ViT: Power-Efficient Approximations of Non-Linearities in Vision Transformers. ISLPED 2024: 1-6 - [i17]Mustafa Altay Karamuftuoglu, Beyza Zeynep Ucpinar, Arash Fayyazi, Sasan Razmkhah, Mehdi Kamal, Massoud Pedram:
Scalable Superconductor Neuron with Ternary Synaptic Connections for Ultra-Fast SNN Hardware. CoRR abs/2402.16384 (2024) - [i16]Mohammad Erfan Sadeghi, Arash Fayyazi, Seyedarmin Azizi, Massoud Pedram:
PEANO-ViT: Power-Efficient Approximations of Non-Linearities in Vision Transformers. CoRR abs/2406.14854 (2024) - [i15]Mohammad Erfan Sadeghi, Arash Fayyazi, Suhas Somashekar, Massoud Pedram:
CHOSEN: Compilation to Hardware Optimization Stack for Efficient Vision Transformer Inference. CoRR abs/2407.12736 (2024) - 2023
- [j4]Soheil Nazar Shahsavani
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 16(2): 17:1-17:25 (2023) - [c14]Gokul Subramanian Ravi
Better Than Worst-Case Decoding for Quantum Error Correction. ASPLOS (2) 2023: 88-102 - [c13]Jingkai Hong, Arash Fayyazi, Amirhossein Esmaili, Mahdi Nazemi, Massoud Pedram:
Algorithms and Hardware for Efficient Processing of Logic-based Neural Networks. DAC 2023: 1-6 - [i14]Jung Hwan Heo, Arash Fayyazi, Mahdi Nazemi, Massoud Pedram:
A Fast Training-Free Compression Framework for Vision Transformers. CoRR abs/2303.02331 (2023) - [i13]Jingkai Hong, Arash Fayyazi, Amirhossein Esmaili, Mahdi Nazemi, Massoud Pedram:
Algorithms and Hardware for Efficient Processing of Logic-based Neural Networks. CoRR abs/2304.06299 (2023) - [i12]Jung Hwan Heo, Seyedarmin Azizi, Arash Fayyazi, Mahdi Nazemi, Massoud Pedram:
SNT: Sharpness-Minimizing Network Transformation for Fast Compression-friendly Pretraining. CoRR abs/2305.04526 (2023) - [i11]Arash Fayyazi, Mahdi Nazemi, Armin Abdollahi, Massoud Pedram:
BlendNet: Design and Optimization of a Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions. CoRR abs/2307.03784 (2023) - [i10]Seyedarmin Azizi, Mahdi Nazemi, Arash Fayyazi, Massoud Pedram:
Sensitivity-Aware Mixed-Precision Quantization and Width Optimization of Deep Neural Networks Through Cluster-Based Tree-Structured Parzen Estimation. CoRR abs/2308.06422 (2023) - 2022
- [c12]Jung Hwan Heo, Arash Fayyazi, Amirhossein Esmaili, Massoud Pedram:
Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators. ISLPED 2022: 3:1-3:6 - [i9]Jung Hwan Heo, Arash Fayyazi, Amirhossein Esmaili, Massoud Pedram:
Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators. CoRR abs/2207.00068 (2022) - [i8]Soheil Nazar Shahsavani, Arash Fayyazi, Mahdi Nazemi, Massoud Pedram:
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis. CoRR abs/2208.00302 (2022) - [i7]Gokul Subramanian Ravi, Jonathan M. Baker, Arash Fayyazi, Sophia Fuhui Lin, Ali Javadi-Abhari, Massoud Pedram, Frederic T. Chong:
Have your QEC and Bandwidth too!: A lightweight cryogenic decoder for common / trivial errors, and efficient bandwidth + execution management otherwise. CoRR abs/2208.08547 (2022) - 2021
- [c11]Hitarth Kanakia, Mahdi Nazemi, Arash Fayyazi, Massoud Pedram:
ESPRESSO-GPU: Blazingly Fast Two-Level Logic Minimization. DATE 2021: 1038-1043 - [c10]Mahdi Nazemi, Arash Fayyazi, Amirhossein Esmaili, Atharva Khare, Soheil Nazar Shahsavani, Massoud Pedram:
NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic. FCCM 2021: 266-267 - [c9]Mustafa Munir
qMC: A Formal Model Checking Verification Framework For Superconducting Logic. ACM Great Lakes Symposium on VLSI 2021: 259-264 - [i6]Mahdi Nazemi, Arash Fayyazi, Amirhossein Esmaili, Atharva Khare, Soheil Nazar Shahsavani, Massoud Pedram:
NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic. CoRR abs/2104.05421 (2021) - 2020
- [c8]Mahdi Nazemi, Amirhossein Esmaili, Arash Fayyazi, Massoud Pedram:
SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional Learning. ICCAD 2020: 89:1-89:9 - [c7]Arash Fayyazi, Amirhossein Esmaili, Massoud Pedram:
HIPE-MAGIC: a technology-aware synthesis and mapping flow for highly parallel execution of memristor-aided LoGIC. ISLPED 2020: 235-240 - [i5]Arash Fayyazi, Shahin Nazarian, Massoud Pedram:
Logic Verification of Ultra-Deep Pipelined Beyond-CMOS Technologies. CoRR abs/2005.13735 (2020) - [i4]Arash Fayyazi, Amirhossein Esmaili, Massoud Pedram:
HIPE-MAGIC: A Technology-Aware Synthesis and Mapping Flow for HIghly Parallel Execution of Memristor-Aided LoGIC. CoRR abs/2006.03269 (2020) - [i3]Mahdi Nazemi, Amirhossein Esmaili, Arash Fayyazi, Massoud Pedram:
SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional Learning. CoRR abs/2007.15222 (2020)
2010 – 2019
- 2019
- [j3]Mohammad Ansari
OCTAN: An On-Chip Training Algorithm for Memristive Neuromorphic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(12): 4687-4698 (2019) - [c6]Arash Fayyazi, Soheil Shababi, Pierluigi Nuzzo, Shahin Nazarian, Massoud Pedram:
Deep Learning-Based Circuit Recognition Using Sparse Mapping and Level-Dependent Decaying Sum Circuit Representations. DATE 2019: 638-641 - [c5]Karunveer Singh, Rishabh Gupta, Vikram Gupta, Arash Fayyazi, Massoud Pedram, Shahin Nazarian:
A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning. ACM Great Lakes Symposium on VLSI 2019: 367-370 - [c4]Shahin Nazarian, Arash Fayyazi, Massoud Pedram:
qCG: A Low-Power Multi-Domain SFQ Logic Design and Verification Framework. ICCD 2019: 446-449 - [c3]Alvin D. Wong, Kevin Su, Hang Sun, Arash Fayyazi, Massoud Pedram, Shahin Nazarian:
VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology. ISQED 2019: 224-230 - [c2]Arash Fayyazi, Souvik Kundu
CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity. ISVLSI 2019: 465-470 - [i2]Alvin D. Wong, Kevin Su, Hang Sun, Arash Fayyazi, Massoud Pedram, Shahin Nazarian:
VeriSFQ - A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology. CoRR abs/1903.07025 (2019) - 2018
- [j2]Arash Fayyazi
An Ultra Low-Power Memristive Neuromorphic Circuit for Internet of Things Smart Sensors. IEEE Internet Things J. 5(2): 1011-1022 (2018) - [j1]Mohammad Ansari
PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1602-1613 (2018) - [i1]Arash Fayyazi, Souvik Kundu, Shahin Nazarian, Peter A. Beerel, Massoud Pedram:
SpRRAM: A Predefined Sparsity Based Memristive Neuromorphic Circuit for Low Power Application. CoRR abs/1809.03476 (2018) - 2016
- [c1]Reza Zendegani, Mehdi Kamal, Arash Fayyazi, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram:
SEERAD: A high speed yet energy-efficient rounding-based approximate divider. DATE 2016: 1481-1484
Coauthor Index
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