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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 13
Volume 13, Number 1, January 1994
- Jason Cong, Yuzheng Ding:
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. 1-12 - Martine D. F. Schlag, Jackson Kong, Pak K. Chan:
Routability-driven technology mapping for lookup table-based FPGA's. 13-26 - Lars W. Hagen, Andrew B. Kahng, Fadi J. Kurdahi, Champaka Ramachandran:
On the intrinsic Rent parameter and spectra-based partitioning methodologies. 27-37 - Majid Sarrafzadeh, Kuo-Feng Liao, Chak-Kuen Wong:
Single-layer global routing. 38-47 - Reiji Suda, Ryotaro Kamikawai, Yasuo Wada, Willy Hioe, Mutsumi Hosoya, Eiichi Goto:
QFP wiring problem-introduction and analytical considerations. 48-56 - Kurt Antreich, Helmut E. Graeb, Claudia U. Wieser:
Circuit analysis and optimization driven by worst-case distances. 57-71 - Franz Fasching, Walter Tuppa, Siegfried Selberherr
:
VISTA-the data level. 72-81 - Martin D. Giles, Duane S. Boning, Goodwin R. Chin, Walter C. Dietrich Jr., Michael S. Karasick, Mark E. Law, Purnendu K. Mozumder, Lee R. Nackman, V. T. Rajan, Duncan M. Hank Walker, Robert H. Wang, Alexander S. Wong:
Semiconductor wafer representation for TCAD. 82-95 - Jaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson:
Algorithms for the transient simulation of lossy interconnect. 96-104 - W. W. Wong, Juin J. Liou:
JFET circuit simulation using SPICE implemented with an improved model. 105-109 - So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu:
A multi-probe approach for MCM substrate testing. 110-121 - Filip Van Aelten, Jonathan Allen, Srinivas Devadas:
Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs. 122-134
Volume 13, Number 2, February 1994
- Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin:
Performance-driven interconnection optimization for microarchitecture synthesis. 137-149 - Zebo Peng, Krzysztof Kuchcinski
Automated transformation of algorithms into register-transfer level implementations. 150-166 - June-Kyung Rho, Gary D. Hachtel, Fabio Somenzi, Reily M. Jacoby:
Exact and heuristic algorithms for the minimization of incompletely specified state machines. 167-177 - Yang Cai, Martin D. F. Wong
On shifting blocks and terminals to minimize channel density. 178-186 - Masayuki Terai, Kazuo Nakajima, Kazuhiro Takahashi, Koji Sato:
A new approach to over-the-cell channel routing with three layers. 187-200 - Hans Kosina, Siegfried Selberherr
A hybrid device simulator that combines Monte Carlo and drift-diffusion analysis. 201-210 - Larry G. Jones, David T. Blaauw:
A cache-based method for accelerating switch-level simulation. 211-218 - Edward W. Scheckler, Andrew R. Neureuther:
Models and algorithms for three-dimensional topography simulation with SAMPLE-3D. 219-230 - Andrew T. Yang, Yu Liu, Jack T. Yao:
An efficient nonquasi-static diode model for circuit simulation. 231-239 - Irith Pomeranz, Sudhakar M. Reddy:
An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits. 240-250 - Irith Pomeranz, Sudhakar M. Reddy:
SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes. 251-263 - Georg Pelz, Uli Roettcher:
Pattern matching and refinement hybrid approach to circuit comparison. 264-276
Volume 13, Number 3, March 1994
- Miodrag Potkonjak, Jan M. Rabaey:
Optimizing resource utilization using transformations. 277-292 - Philip B. M. Wolbert, Gerhard K. M. Wachutka, Benno H. Krabbenborg, Ton J. Mouthaan:
Nonisothermal device simulation using the 2D numerical process/device simulator TRENDY and application to SOI-devices. 293-302 - Ting-Hai Chao, Yu-Chin Hsu:
Rectilinear Steiner tree construction by local and global refinement. 303-309 - Ronald J. G. Goossens, Stephen G. Beebe, Zhiping Yu, Robert W. Dutton:
An automatic biasing scheme for tracing arbitrarily shaped I-V curves. 310-317 - Shiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu:
Timed Boolean calculus and its applications in timing analysis. 318-337 - Peter M. Maurer, Yun Sik Lee:
Gateways: a technique for adding event-driven behavior to compiled simulations. 338-352 - Bechir Ayari, Bozena Kaminska:
A new dynamic test vector compaction for automatic test pattern generation. 353-358 - Víctor H. Champac, Antonio Rubio, Joan Figueras:
Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing. 359-369 - Beyin Chen, Chung-Len Lee:
A complement-based fast algorithm to generate universal test sets for multi-output functions. 370-377 - Irith Pomeranz, Sudhakar M. Reddy:
On achieving complete fault coverage for sequential machines. 378-386 - Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita:
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits. 387-395 - Russell Kao, Mark Horowitz:
Eliminating redundant DC equations for asymptotic waveform evaluation. 396-397
Volume 13, Number 4, April 1994
- Jerry R. Burch, Edmund M. Clarke, David E. Long, Kenneth L. McMillan, David L. Dill:
Symbolic model checking for sequential circuit verification. 401-424 - Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu:
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. 425-438 - Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski:
A transformation-based method for loop folding. 439-450 - Minjoong Rim
Lower-bound performance estimation for the high-level synthesis scheduling problem. 451-458 - Mark D. Aagaard, Miriam Leeser
PBS: proven Boolean simplification. 459-470 - Ahmed S. Desouki, Young-June Park, Hong-Shick Min:
A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays. 471-481 - Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury:
Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices. 482-493 - Rupert Howes, William Redman-White, Ken G. Nichols, Peter J. Mole, Michael J. Robinson, Simon Bird:
An SOS MOSFET model based on calculation of the surface potential. 494-506 - Tatsuya Kunikiyo, Katsuyoshi Mitsui, Masato Fujinaga, Tetsuya Uchida, Norihiko Kotani:
Reverse short-channel effect due to lateral diffusion of point-defect induced by source/drain ion implantation. 507-514 - Henry Cox, Janusz Rajski:
On necessary and nonconflicting assignments in algorithmic test pattern generation. 515-530 - Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima:
Fault simulation for multiple faults by Boolean function manipulation. 531-535
Volume 13, Number 5, May 1994
- Said Amellal, Bozena Kaminska:
Functional synthesis of digital systems with TASS. 537-552 - Daniel Brand, Vijay S. Iyengar:
Identification of redundant delay faults. 553-565 - Kaushik De, Balkrishna Ramkumar, Prithviraj Banerjee:
A portable parallel algorithm for logic synthesis using transduction. 566-580 - P. N. Lam, Hon Fung Li, S. C. Leung:
Optimization of state encoding in distributed circuits. 581-588 - Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Satisfaction of input and output encoding constraints. 589-602 - C. Y. Roger Chen, Cliff Yungchin Hou, Uminder Singh:
Optimal algorithms for bubble sort based non-Manhattan channel routing. 603-609 - Mitiko Miura-Mattausch:
Analytical MOSFET model for quarter micron technologies. 610-615 - Kenny K. H. Toh, Andrew R. Neureuther, Edward W. Scheckler:
Algorithms for simulation of three-dimensional etching. 616-624 - Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer:
SWiTEST: a switch level test generation system for CMOS combinational circuits. 625-637 - Kuo-Feng Liao, Majid Sarrafzadeh:
Correction to "Boundary single-layer routing with movable terminals". 638 - Weiwei Mao, Michael D. Ciletti:
Reducing correlation to improve coverage of delay faults in scan-path design. 638-646 - Prem R. Menon, Hitesh Ahuja, Mohan Harihara:
Redundancy identification and removal in combinational circuits. 646-651 - Michael Nicolaidis:
Fault secure property versus strongly code disjoint checkers. 651-658 - Janusz A. Starzyk:
Hierarchical analysis of high frequency interconnect networks. 658-664
Volume 13, Number 6, June 1994
- Jan M. Rabaey, Miodrag Potkonjak:
Estimating implementation bounds for real time DSP application specific circuits. 669-683 - Tae Won Cho, Sam S. Pyo, J. Robert Heath:
PARALLEX: a parallel approach to switchbox routing. 684-693 - Alessandro De Gloria, Paolo Faraboschi
Block placement with a Boltzmann Machine. 694-701 - Y. Apanovich, Eugeny D. Lyumkis, Boris S. Polsky, Alex I. Shur, Peter A. Blakey:
Steady-state and transient analysis of submicron devices using energy balance and simplified hydrodynamic models. 702-711 - Udaya A. Ranawake, Carl Huster, Patrick M. Lenders, Stephen Marshall Goodnick:
PMC-3D: a parallel three-dimensional Monte Carlo semiconductor device simulator. 712-724 - Jason Yao-Tsung Tsai, Kuo-Don Hong, Yin-Lun Yuan:
An efficient analytical model for calculating trapped charge in amorphous silicon. 725-728 - Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage
Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications. 729-736 - Sina Balkir, Mehmet Yanilmaz, Martin A. Plonus:
Numerical integration using Bezier splines. 737-745 - Anirudh Devgan, Ronald A. Rohrer:
Adaptively controlled explicit simulation. 746-762 - Curtis L. Ratzlaff, Lawrence T. Pillage
RICE: rapid interconnect circuit evaluation using AWE. 763-776 - Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab:
Structural and behavioral synthesis for testability techniques. 777-785 - Silvano Gai, Pier Luca Montessoro:
Creator: new advanced concepts in concurrent simulation. 786-795 - Linda S. Milor
Minimizing production test time to detect faults in analog circuits. 796-813 - Srinivas Devadas, Kurt Keutzer, Sharad Malik
Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. 814-822 - Hsu-Chun Yen:
On multiterminal single bend wirability. 822-826
Volume 13, Number 7, July 1994
- Balkrishna Ramkumar, Prithviraj Banerjee:
ProperCAD: A portable object-oriented parallel environment for VLSI CAD. 829-842 - D. L. Springer, Donald E. Thomas:
Exploiting the special structure of conflict and compatibility graphs in high-level synthesis. 843-856 - Siu-Wing Cheng, Hsi-Chuan Chen, David Hung-Chang Du, Andrew Lim
The role of long and short paths in circuit performance optimization. 857-864 - June-Kyung Rho, Fabio Somenzi:
Don't care sequences and the optimization of interacting finite state machines. 865-874 - Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Circuit structure relations to redundancy and delay. 875-883 - Shun-Shii Lin:
Constant-time algorithms for the channel assignment problem on processor arrays with reconfigurable bus systems. 884-890 - Xiaoyu Song, Xuehou Tan:
An optimal channel-routing algorithm in the times square model. 891-898 - Woo-Sung Choi, Jae-Gyung Ahn, Young-June Park, Hong-Shick Min, Chang-Gyu Hwang:
A time dependent hydrodynamic device simulator SNU-2D with new discretization scheme and algorithm. 899-908 - Li-Ren Liu, David Hung-Chang Du, Hsi-Chuan Chen:
An efficient parallel critical path algorithm. 909-919 - Vivek Chickermane, Jaushin Lee, Janak H. Patel:
Addressing design for testability at the architectural level. 920-934 - Rochit Rajsuman:
A new testing method for EEPLA. 935-939 - Jos van Sas, Francky Catthoor, Hugo De Man:
Cellular automata based deterministic self-test strategies for programmable data paths. 940-949 - Sharad Malik
Analysis of cyclic combinational circuits. 950-956
Volume 13, Number 8, August 1994
- Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula:
EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition. 959-975 - Jagannathan Narasimham, Kazuo Nakajima, Chong S. Rim, Anton T. Dahbura:
Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements. 976-986 - C. Thomas Gray, Wentai Liu, Ralph K. Cavin III:
Timing constraints for wave-pipelined systems. 987-1004 - Prabhat Jain, Ganesh Gopalakrishnan:
Efficient symbolic simulation-based verification using the parametric form of Boolean expressions. 1005-1015 - Li-Ren Liu, Hsi-Chuan Chen, David Hung-Chang Du:
The calculation of signal stable ranges in combinational circuits. 1016-1023 - Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel:
Exact calculation of synchronizing sequences based on binary decision diagrams. 1024-1034 - Gwo-Chung Tai, Can E. Korman, Isaak D. Mayergoyz:
A parallel-in-time method for the transient simulation of SOI devices with drain current overshoots. 1035-1044 - Wing Ning:
Strongly NP-hard discrete gate-sizing problems. 1045-1051 - Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel:
An observability enhancement approach for improved testability and at-speed test. 1051-1056 - Jacob Savir, Srinivas Patil:
Broad-side delay test. 1057-1064 - Shun-Lin Su, Charles H. Barry, Chi-Yuan Lo:
A space-efficient short-finding algorithm [VLSI layouts]. 1065-1068
Volume 13, Number 9, September 1994
- Arun Achyuthan, Mohamed I. Elmasry:
Mixed analog/digital hardware synthesis of artificial neural networks. 1073-1087 - Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
Spectral K-way ratio-cut partitioning and clustering. 1088-1096 - Brian Lockyear, Carl Ebeling:
Optimal retiming of level-clocked circuits using symmetric clock schedules. 1097-1109 - Chi-Ying Tsui
Power efficient technology decomposition and mapping under an extended power consumption model. 1110-1122 - Farid N. Najm:
Low-pass filter for computing the transition density in digital circuits. 1123-1131 - Sherif H. K. Embabi, R. Damodaran:
Delay models for CMOS, BiCMOS and BiNMOS circuits and their applications for timing simulations. 1132-1142 - Wolfgang Kunz, Dhiraj K. Pradhan:
Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization. 1143-1158 - Tai-Yu Chou, Zoltan J. Cendes:
Capacitance calculation of IC packages using the finite element method and planes of symmetry. 1159-1166 - Sudhir M. Gowda, Bing J. Sheu:
BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits. 1166-1170 - Dimitrios Kagaris, Fillia Makedon, Spyros Tragoudas:
A method for pseudo-exhaustive test pattern generation. 1170-1178 - Ted Stanion, Carl Sechen:
Boolean division and factorization using binary decision diagrams. 1179-1184
Volume 13, Number 10, October 1994
- Konrad Doll, Frank M. Johannes, Kurt Antreich:
Iterative placement improvement by network flow methods. 1189-1200 - King C. Ho, Sarma B. K. Vrudhula:
Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts. 1201-1222 - Ping-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj:
A probabilistic timing approach to hot-carrier effect estimation. 1223-1234 - Minchang Liang, Mark E. Law:
An object-oriented approach to device simulation-FLOODS. 1235-1240 - Dwight L. Woolard, Hong Tian, Michael A. Littlejohn, K. W. Kim
The implementation of physical boundary conditions in the Monte Carlo simulation of electron devices. 1241-1246 - Walter Allegretto, Bing Shen, P. Haswell, Zhongsheng Lai, Alexander M. Robinson:
Numerical modeling of a micromachined thermal conductivity gas pressure sensor. 1247-1256 - Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage
Time-domain macromodels for VLSI interconnect analysis. 1257-1270 - Abdolreza Nabavi-Lishi, Nicholas C. Rumin:
Inverter models of CMOS gates for supply current and delay evaluation. 1271-1279 - TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang:
Logic synthesis for field-programmable gate arrays. 1280-1287 - Jaushin Lee, Janak H. Patel:
Architectural level test generation for microprocessors. 1288-1300 - T. V. Nguyen:
Recursive convolution and discrete time domain simulation of lossy coupled transmission lines. 1301-1305
Volume 13, Number 11, November 1994
- Ganesh Gopalakrishnan, Erik Brunvand, Nick Michell, Steven M. Nowick:
A correctness criterion for asynchronous circuit validation and optimization. 1309-1318 - Amir H. Farrahi, Majid Sarrafzadeh:
Complexity of the lookup-table minimization problem for FPGA technology mapping. 1319-1332 - S. Parameswaran, M. F. Schulz:
Computer-aided selection of components for technology-independent specifications. 1333-1350 - Jeff Griffith, Gabriel Robins, Jeffrey S. Salowe, Tongtong Zhang:
Closing the gap: near-optimal Steiner trees in polynomial time. 1351-1365 - Dirk Theune, Ralf Thiele, Werner John, Thomas Lengauer:
Robust methods for EMC-driven routing. 1366-1378 - M. Karim Moallemi, Hui Zhang:
A general numerical procedure for multilayer multistep IC process simulation. 1379-1390 - Giorgio Casinovi, Jeen-Mo Yang:
Multi-level simulation of large analog systems containing behavioral models. 1391-1399 - Alberto Leone, Antonio Gnudi
Hydrodynamic simulation of semiconductor devices operating at low temperature. 1400-1408 - Jun-Fa Mao, Zheng-Fan Li:
Waveform relaxation solution of the ABCD matrices of nonuniform transmission lines for transient analysis. 1409-1412 - S. Wayne Bollinger, Scott F. Midkiff
Test generation for IDDQ testing of bridging faults in CMOS circuits. 1413-1418 - Richard I. Hartley, Albert E. Casavant:
Optimizing pipelined networks of associative and commutative operators. 1418-1425 - Akira Kato, Mitsutaka Katada, Toyoharu Kamiya, Toyoki Ito, Tadashi Hattori:
A rapid, stable decoupled algorithm for solving semiconductor hydrodynamic equations. 1425-1428 - Irith Pomeranz, Sudhakar M. Reddy:
On determining symmetries in inputs of logic circuits. 1428-1434 - Yasunori Sameshima, Yoshihiro Kitamura, Tomoo Fukazawa:
Multiple signature analysis method using fault simulation. 1434-1437
Volume 13, Number 12, December 1994
- Xiaobo Sharon Hu
Minimizing the number of delay buffers in the synchronization of pipelined systems. 1441-1449 - Champaka Ramachandran, Fadi J. Kurdahi
Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications. 1450-1460 - Charles C. Chiang, Chak-Kuen Wong, Majid Sarrafzadeh:
A weighted Steiner tree-based global router with simultaneous length and density minimization. 1461-1469 - Massoud Pedram, Bahman S. Nobandegani, Bryan Preas:
Design and analysis of segmented routing channels for row-based FPGA's. 1470-1479 - Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
A general purpose, multiple-way partitioning algorithm. 1480-1488 - Joe Rodriguez-Tellez, Kahtan A. Mezher
Computationally efficient and accurate capacitance model for the GaAs MESFET for microwave nonlinear circuit design. 1489-1497 - Russell Kao, Mark Horowitz:
Timing analysis for piecewise linear Rsim. 1498-1512 - Sanjay L. Manney, Michel S. Nakhla, Qi-Jun Zhang:
Analysis of nonuniform, frequency-dependent high-speed interconnects using numerical inversion of Laplace transform. 1513-1525 - Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage
Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. 1526-1535 - Sachin S. Sapatnekar
Convexity-based algorithms for design centering. 1536-1549 - Karl Fuchs, Michael Pabst, Torsten Rössel:
RESIST: a recursive test pattern generation algorithm for path delay faults considering various test classes. 1550-1562 - Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
An edge-based heuristic for Steiner routing. 1563-1568
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