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Tai-Ming Parng
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2000 – 2009
- 2001
- [j10]Shang-Lin Hsieh, Tai-Ming Parng:
A new scheme for rectifying recognition results of printed chinese characters. Pattern Recognit. 34(11): 2121-2132 (2001)
1990 – 1999
- 1996
- [j9]Hung-Pin Chen, Tai-Ming Parng:
A new approach of multi-stage fuzzy logic inference. Fuzzy Sets Syst. 78(1): 51-72 (1996) - [j8]Chiung-San Lee, Tai-Ming Parng:
Performance Modeling and Evaluation of a Two-Dimensional Disk Array System. J. Parallel Distributed Comput. 38(1): 16-27 (1996) - [j7]Chiung-San Lee, Tai-Ming Parng:
A Subsystem-Oriented Performance Analysis Methodology for Shared-Bus Multiprocessors. IEEE Trans. Parallel Distributed Syst. 7(7): 755-767 (1996) - 1995
- [j6]Chiung-San Lee, Tai-Ming Parng:
Bottleneck Identification Methodology for Performance-Oriented Design of Shared-Bus Multiprocessors. IEICE Trans. Inf. Syst. 78-D(8): 982-991 (1995) - [j5]Wen-Chung Kao, Tai-Ming Parng:
Cross point assignment with global rerouting for general-architecture designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 337-348 (1995) - 1994
- [j4]Shiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu:
Timed Boolean calculus and its applications in timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3): 318-337 (1994) - [c12]Jui-Ching Shyur, Hung-Pin Chen, Tai-Ming Parng:
On Testing Wave Pipelined Circuits. DAC 1994: 370-374 - [c11]Chiung-San Lee, Tai-Ming Parng, Jew-Chin Lee, Cheng-Nan Tsai, Kwo-Jean Farn, Lung-Chung Chang, Te-Yu Chung, Lu-Ping Chen:
Performances Modeling and Evaluation for the XMP Shared-Bus Multiprocessor Architecture. ICPADS 1994: 446-453 - [c10]Chiung-San Lee, Tai-Ming Parng, Jew-Chin Lee, Cheng-Nan Tsai, Kwo-Jean Farn:
Performance analysis of the XDAC disk array system. SPDP 1994: 620-627 - 1993
- [j3]Gia-Shuh Jang, Feipei Lai, Bor-Wei Jiang, Tai-Ming Parng, Li-Hua Chien:
Intelligent stock trading system with price trend prediction and reversal recognition using dual-module neural networks. Appl. Intell. 3(3): 225-248 (1993) - [j2]Yi-Fan Ke, Tai-Ming Parng:
The Guard Heuristic: Legal Move Ordering with Forward Game-Tree Pruning. J. Int. Comput. Games Assoc. 16(2): 76-85 (1993) - [c9]Shiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu:
A Polynomial-Time Heuristic Approach to Approximate a Solution to the False Path Problem. DAC 1993: 118-122 - 1991
- [j1]Yeu-Shen Jehng, Liang-Gee Chen
, Tai-Ming Parng:
ASG: Automatic schematic generator. Integr. 11(1): 11-27 (1991) - [c8]Chin-Yuan Kuo, Liang-Gee Chen, Tai-Ming Parng:
An automatic synthesizer for CMOS operational amplifiers. EURO-DAC 1991: 470-474 - [c7]Shiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu:
A New Approach to Solving False Path Problem in Timing Analysis. ICCAD 1991: 216-219 - 1990
- [c6]Feipei Lai, Lea-Ming Tzeng, Thom-Ling Chang, Tai-Ming Parng:
MARS Performance Evaluation with Different Interconnection Networks. ICSI 1990: 248-257 - [c5]Feipei Lai, Chyuan-Yow Wu, Tai-Ming Parng:
A memory management unit and cache controller for the MARS system. MICRO 1990: 200-208
1980 – 1989
- 1989
- [c4]Tai-Ming Parng, Ren-Song Tsay:
A new approach to sea-of-gates global routing. ICCAD 1989: 52-55 - [c3]Hung-Chang Lee, Feipei Lai, Jenn-Yuan Tsai, Tai-Ming Parng, Yu-Gang Li:
MARS-a RISC-based architecture for LISP. TAI 1989: 198-206 - 1988
- [c2]Gwo-Dong Chen, Tai-Ming Parng:
A Database Management System for a VLSI Design System. DAC 1988: 257-262 - 1984
- [c1]Tai-Ming Parng, Shing-Chong Chang:
Logical Design of High Level Protocols for Local Area Network. ICDCS 1984: 166-172
Coauthor Index
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