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ReConFig 2006: San Luis Potosi, Mexico
- René Cumplido-Parra, César Torres-Huitzil, Andrés D. García:
2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006, San Luis Potosi, Mexico, September 20-22, 2006. IEEE Computer Society 2006, ISBN 1-4244-0690-0
Reconfigurable Architectures I
- Javier Castillo, Pablo Huerta, César Pedraza, José Ignacio Martínez:
A Self-Reconfigurable Multimedia Player on FPGA. 6-11 - Marcelo Götz
, Florian Dittmann:
Reconfigurable Microkernel-based RTOS: Mechanisms and Methods for Run-Time Reconfiguration. 12-19 - Marcos Vinícius da Silva, Ricardo S. Ferreira, Alisson Garcia, João M. P. Cardoso
Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures. 20-29 - Jacob A. Bower, David B. Thomas, Wayne Luk, Oskar Mencer:
A Reconfigurable Simulation Framework for Financial Computation. 30-38 - Andres Cicuttin, Maria Liz Crespo
A Block-Based Open Source Approach for a Reconfigurable Virtual Instrumentation Platform Using FPGA Technology. 39-46 - Sumanta Chaudhuri
FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems. 47-55
Tools
- AbdelHalim Samahi, El-Bay Bourennane, Sami Boukhechem:
Communication Interface Generation For HW/SW Architecture In The STARSoC Environment. 58-63 - Jorge Luiz e Silva, Eduardo Marques
Executing Algorithms for Dynamic Dataflow Reconfigurable Hardware -The Operators Protocol. 64-70 - Julio A. de Oliveira Filho, Thomas Schweizer, Tobias Oppold, Tommy Kuhn, Wolfgang Rosenstiel:
Tuning Coarse-Grained Reconfigurable Architectures towards an Application Domain. 71-77 - Jorge Alberto Surís, Peter M. Athanas:
Exploring Non-Traditional Hardware-Software Interaction. 78-85 - Heng Tan, Ronald F. DeMara
A Physical Resource Management Approach to Minimizing FPGA Partial Reconfiguration Overhead. 86-90
Applications 1: Bio-inspired systems
- Nilton B. Armstrong, Heitor S. Lopes
Preliminary Steps Towards Protein Folding Prediction Using Reconfigurable Computing. 92-98 - Guilherme Luiz Moritz
Implementation of a Parallel Algorithm for Protein Pairwise Alignment Using Reconfigurable Computing. 99-105 - Rashad S. Oreifej, Carthik A. Sharma, Ronald F. DeMara
Expediting GA-Based Evolution Using Group Testing Techniques for Reconfigurable Hardware. 106-113 - Jorge Peña, Mauricio Vanegas
Digital Hardware Architectures of Kohonen's Self Organizing Feature Maps with Exponential Neighboring Function. 114-121 - Carlos E. Gutiérrez Salmeron, Andrés David García García, Reynaldo Félix Acuña:
Bio - Inspired & Traditional Approaches to Obtain Fault Tolerance. 122-129
Physical design
- Timothy Lantz, Eric Peskin:
A QCA Implementation of a Configurable Logic Block for an FPGA. 132-141 - Ameet Chavan, Gaurav Dukle, Ben Graniello, Eric W. MacDonald
Robust Ultra-Low Power Subthreshold Logic Flip-Flop Design for Reconfigurable Architectures. 142-148 - Marcos R. de Alba-Rosano, Andrés David García García:
Measuring Leakage Power in Nanometer CMOS 6T-SRAM Cells. 149-155
Applications II
- Maurice Keller, Robert Ronan, William P. Marnane
A GF(24m) Inverter and its Application in a Reconfigurable Tate Pairing Processor. 158-167 - Ahmed Elhossini, Shawki Areibi, Robert D. Dony:
An FPGA Implementation of the LMS Adaptive Filter for Audio Processing. 168-175 - Miguel Morales-Sandoval
GF(2m) Arithmetic Modules for Elliptic Curve Cryptography. 176-183 - Elvira Martínez de Icaya, Victoria Rodellar, Coral Gonzalez-Concejero, Virginia Peinado, Vicente Angel García:
Design Space Exploration for an Adaptive Noise Cancellation Algorithm. 184-190 - Santos López-Estrada, René Cumplido:
Decision Tree Based FPGA-Architecture for Texture Sea State Classification. 191-197 - Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga:
Realization of the sound space environment for the radiation-tolerant space craft. 198-205
Image and Video Processing
- Steven Bishop, Suresh Rai, Bahadir K. Gunturk
Reconfigurable Implementation of Wavelet Integer Lifting Transforms for Image Compression. 208-216 - Griselda Saldaña
Real Time FPGA-based Architecture for Video Applications. 217-226 - José Martínez
FPGA-based Pipeline Architecture to Transform Cartesian Images into Foveal Images by Using a new Foveation Approach. 227-236 - Julio C. Sosa
Change-driven Image Architecture on FPGA with adaptive threshold for Optical-Flow Computation. 237-243 - Pedro Gómez
Robust cDNA microarray image processing on a hand-held device. 244-248
Reconfigurable Architectures II
- Thorsten von Sydow, Matthias Korb, Bernd Neumann, Holger Blume
Modelling and Quantitative Analysis of Coupling Mechanisms of Programmable Processor Cores and Arithmetic Oriented eFPGA Macros. 252-261 - Florian Dittmann, Achim Rettberg, Raphael Weber:
Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture. 262-269 - Manuel Saldaña, Daniel Nunes, Emanuel Ramalho, Paul Chow:
Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI. 260-279 - Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl:
Datapath and ISA Customization for Soft VLIW Processors. 280-289 - Daniel M. Muñoz
Implementation, Simulation and Validation of Dispatching Algorithms for Elevator Systems. 290-297
Education and Applications III
- René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno, Jose Alberto Vite-Frias, Arturo Garcia-Perez:
8-bit CISC Microprocessor Core for Teaching Applications in the Digital Systems Laboratory. 300-303 - Gerardo Eli Martínez-Torres, J. M. Luna-Rivera
FPGA-Based Educational Platform for Wireless Transmission Using System Generator. 304-313 - Omar Piña-Ramirez, Raquel Valdés-Cristerna, Oscar Yáñez-Suárez
An FPGA Implementation of Linear Kernel Support Vector Machines. 314-319 - Julio C. G. Pimentel:
Implementation of Simulation Algorithms in FPGA for Real Time Simulation of Electrical Networks with Power Electronics Devices. 320-327 - Yogindra Abhyankar, C. Sajish, Yogesh Agarwal, C. R. Subrahmanya, Peeyush Prasad:
High Performance Power Spectrum Analysis Using a FPGA Based Reconfigurable Computing Platform. 328-331 - Ulises S. Mendoza-Camarena, René de Jesús Romero-Troncoso:
VHDL Core for the Computation of the One-Dimensional Discrete Cosine Transform. 332-339
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