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Andrés David García García
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2010 – 2019
- 2013
- [c12]Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García:
A VLSI architecture for the QR decomposition based on the MCGR algorithm. ReConFig 2013: 1-6 - 2012
- [c11]Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García:
A VLSI architecture for the K-best Sphere-Decoder in MIMO systems. ReConFig 2012: 1-6 - 2011
- [c10]Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García:
Analysis of Parallel Sorting Algorithms in K-best Sphere-Decoder Architectures for MIMO Systems. ReConFig 2011: 321-326 - 2010
- [c9]J. Pindter-Medina, Samuel Pichardo, Laura Curiel, Andrés David García García, Jesús Enrique Chong-Quero
:
Multi-channel Driving Systems for Therapeutic Applications Based-on Focused Ultrasound. ReConFig 2010: 168-172
2000 – 2009
- 2006
- [c8]Carlos E. Gutiérrez Salmeron, Andrés David García García, Reynaldo Félix Acuña:
Bio - Inspired & Traditional Approaches to Obtain Fault Tolerance. ReConFig 2006: 122-129 - [c7]Marcos R. de Alba-Rosano, Andrés David García García:
Measuring Leakage Power in Nanometer CMOS 6T-SRAM Cells. ReConFig 2006: 149-155 - [e1]René Cumplido-Parra, César Torres-Huitzil, Andrés D. García:
2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006, San Luis Potosi, Mexico, September 20-22, 2006. IEEE Computer Society 2006, ISBN 1-4244-0690-0 [contents] - 2005
- [c6]Roberto Ramírez Marín, Andrés David García García, Luis Fernando González Pérez, Javier Eduardo González Villarruel:
Hardware Architecture of MAP Algorithm for Turbo Codes Implemented in a FPGA. CONIELECOMP 2005: 70-75 - [c5]Luis Fernando González Pérez, Emmanuel Boutillon, Andrés David García García, Javier Eduardo González Villarruel, Reynaldo Félix Acuña:
VLSI Architecture for the M Algorithm Suited for Detection and Source Coding Applications. CONIELECOMP 2005: 119-124 - [c4]Andrés David García García, Luis Fernando González Pérez, Reynaldo Félix Acuña:
Power Consumption Management on FPGAs. CONIELECOMP 2005: 240-245 - 2000
- [c3]Andrés D. García, Jean-Luc Danger, Wayne P. Burleson:
Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. FPGA 2000: 220 - [c2]Andrés D. García, Wayne P. Burleson, Jean-Luc Danger:
Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. ISCAS 2000: 561-564
1990 – 1999
- 1999
- [c1]Andrés D. García, Wayne P. Burleson, Jean-Luc Danger:
Power Modelling in Field Programmable Gate Arrays (FPGA). FPL 1999: 396-404
Coauthor Index
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