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10th LATW 2009: Rio de Janeiro, Brazil
- 10th Latin American Test Workshop, LATW 2009, Rio de Janeiro, Brazil, March 2-5, 2009. IEEE 2009, ISBN 978-1-4244-4206-5
- Luciano C. Ascari, Lucilia Yoshie Araki, Aurora T. R. Pozo
, Silvia R. Vergilio:
Exploring machine learning techniques for fault localization. 1-6 - Tsuyoshi Iwagaki, Mineo Kaneko:
On the derivation of a minimum test set in high quality transition testing. 1-6 - Paolo Maistri:
Pruning single event upset faults with petri nets. 1-6 - Andre Luiz da Silva Solino, Silvia Regina Vergilio:
Mutation based testing of Web Services. 1-6 - Harold R. Chamorro, C. Bustos, L. A. Lopez:
Adaptive position digital control with deadbeat response for a platform on a mobile vehicle. 1-6 - Cristina Ciprandi Menegotto, Taisy Silva Weber, Raul Fernando Weber:
A practical methodology for experimental fault injection to test complex network-based systems. 1-6 - Thiago Assis, Fernanda Lima Kastensmidt
Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in CMOS 90nm technologies. 1-6 - Franco Leite, Tiago R. Balen, Marcos Hervé, Marcelo Lubaszewski, Gilson I. Wirth
Using Bulk Built-In Current Sensors and recomputing techniques to mitigate transient faults in microprocessors. 1-6 - Marc Messing, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
Using a two-dimensional fault list for compact Automatic Test Pattern Generation. 1-6 - Maksim Jenihhin
High-Level Decision Diagrams based coverage metrics for verification and test. 1-6 - Torgan Siqueira, Bruno Coswig Fiss, Raul Weber, Sérgio Luis Cechin, Taisy Silva Weber:
Applying FIRMAMENT to test the SCTP communication protocol under network faults. 1-6 - José Peralta, Marcelo Costamagna, Gabriela Peretti
Estimating the quality of Oscillation-Based Test for detecting parametric faults. 1-6 - Maurício Banaszeski da Silva
NBTI-aware technique for transistor sizing of high-performance CMOS gates. 1-5 - Alex D. B. Alberto, Adenilso Simão:
Minimization of incompletely specified finite state machines based on distinction graphs. 1-6 - Marta Portela-García
Study of SEU effects in a Turbo Decoder Bit Error Rate. 1-5 - Mounir Benabdenbi, François Pêcheux, Etienne Faure:
On-line test and monitoring of multi-processor SoCs: A software-based approach. 1-6 - Sergei Devadze
Turning JTAG inside out for fast extended test access. 1-6 - Eduardo Ribeiro da Silva, F. Costa, Frank Herman Behrens
Analog test bus architecture for small die size and limited pin count devices with internal IPs testability emphasis. 1-6 - Marcos Barcellos Hervé, Érika F. Cota, Fernanda Lima Kastensmidt
NoC interconnection functional testing: Using boundary-scan to reduce the overall testing time. 1-6 - Ellen Souza, Cristine Gusmão, Keldjan Alves, Julio Venancio, Renata Cristina Faray Melo:
Measurement and control for risk-based test cases and activities. 1-6 - Marcelo A. Cappelletti, Ariel P. Cédola
Study of radiation effects on PIN photodiodes with deep-trap levels using computer modeling. 1-6 - Lucieli Tolfo Beque, Thiago Dai Pra, Érika F. Cota:
Testing requirements for an embedded operating system: The exception handling case study. 1-6 - Liana Silva, Sérgio Soares
Analyzing structure-based techniques for test coverage on a J2ME software product line. 1-6 - Raimund Ubar
Investigations of the diagnosibility of digital networks with BIST. 1-6 - Dieison Antonello Deprá, Bruno Zatt, Sergio Bampi
A method for HW functional verification through HW/SW co-simulation in complex systems: H.264/AVC decoder as case study. 1-6 - Ashkan Eghbal, Hamid R. Zarandi, Pooria M. Yaghini:
Fault tolerance assessment of PIC microcontroller based on fault injection. 1-6 - Taisy Silva Weber, Juliano Cardoso Vacaro, Torgan Flores de Siqueira, Ingrid Jansch-Pôrto:
Generating non-uniform distributions for fault injection to emulate real network behavior in test campaigns. 1-6 - Thiago Nunes Coelho Cardoso, José Augusto Miranda Nacif, Antônio Otávio Fernandes, Claudionor Nunes Coelho:
BugTracer: A system for integrated circuit development tracking and statistics retrieval. 1-4 - Santiago Martin Sondón
Radiation damage characterization of digital integrated circuits. 1-5 - Costas Argyrides, Carlos Arthur Lang Lisbôa, Dhiraj K. Pradhan, Luigi Carro
Single element correction in sorting algorithms with minimum delay overhead. 1-6 - Carlos Arthur Lang Lisbôa, Carmela Noro Grando, Álvaro Freitas Moreira, Luigi Carro
Using software invariants for dynamic detection of transient errors. 1-6 - Ezequiel Brac, Pablo A. Ferreyra, Raoul Velazco, Carlos A. Marqués:
Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications. 1-5 - Cristiano Rodrigues:
A case study for Formal Verification of a timing co-processor. 1-6 - Cristina Meinhardt
Recovery scheme for hardening system on programmable chips. 1-6 - Jorge Semião
Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment. 1-6 - Roberto Gómez, Víctor H. Champac, Chuck Hawkins, Jaume Segura
A modern look at the CMOS stuck-open fault. 1-6 - Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Execution time reduction of Differential Power Analysis experiments. 1-5 - Eduardo Ribeiro da Silva, F. Costa, Frank Herman Behrens
Using mixed-mode test bus architecture to RF-based fault injection analysis and EMC fault debug. 1-6
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