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ISOCC 2019: Jeju, South Korea
- 2019 International SoC Design Conference, ISOCC 2019, Jeju, Korea (South), October 6-9, 2019. IEEE 2019, ISBN 978-1-7281-2478-0
- Ko-Chi Kuo:
A 10-bit 250 MS/s Binary Search and Two channel SAR ADC by a two-bit per Conversion with Error Tolerance Ability. 1-2 - Jun-Young Kil, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Gil-Cho Ahn:
A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application. 7-8 - Hyunsung Kim, Juin Lim, Wonbin Hong, Joonho Park, Young-Seok Kim, Mijung Kim, Youngjoo Lee
:
Design of a Low-Power BLE5-Based Wearable Device for Tracking Movements of Football Players. 11-12 - Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim:
Optimization of Null Convenction Logic Using Gate Diffusion Input. 21-22 - Hyounghun Joe, Cheolsoo Park, Hyungtak Kim, Youngmin Kim:
Lower-part Stochastic Unipolar Adder to Improve Computation Accuracy. 23-24 - Sunghye Park
Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU. 25-26 - Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim:
Area Efficient Multi-Threshold Null Convenction Logic. 27-28 - Soyeon Kim, Byeonghyeon Kim, Yongho Lee, Seungsoo Kim, Hyunchol Shin:
A 28GHz Direct Conversion Receiver in 65nm CMOS for 5G mmWave Radio. 29-30 - Byeonghyeon Kim, Soyeon Kim, Yongho Lee, Seungsoo Kim, Hyunchol Shin:
A 28GHz Quadrature Up-conversion Transmitter in 65nm CMOS for 5G mmWave Radio. 31-32 - Xiang Gao:
Low Jitter and Low Power PLL：Towards The Utopia. 38-39 - Jaeduk Han, Eric Chang, Elad Alon:
Design and Automatic Generation of High-Speed Circuits for Wireline Communications. 40-41 - Heejae Hwang, Jongsun Kim:
A Low-Power 20 Gbps Multi-phase MDLL-based Digital CDR with Receiver Equalization. 42-43 - Ghil-Geun Oh, Jong-Ho Eun, Shin-Young Chung, Brandon Lee:
Advanded Design Verification and Debugging Techniques Based on Optical Fault Isolation Method. 44-45 - Kenta Nishiguchi, Toshiyuki Inoue
Optimization Technique of Memory Traffic for FPGA-Based Image Processing System. 46-47 - Kana Shimada, Takuma Hikida, Hiroki Nishikawa, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Scheduling of Malleable Tasks with DMA-based Communication. 48-49 - Ryohei Nozaki, Hiroki Nishikawa, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Function-Level Module Sharing in High-Level Synthesis. 50-51 - Chia-Chun Tsai:
Performance Improvement for Stacked-Layer Data Bus Reconstruction on Complete Timing Period. 52-53 - Tian Guo, Jiho Moon, Jeongjin Roh:
A Power Supply Rejection Compensated External Capacitor-Less Low Drop-Out Regulator. 54-55 - Kun-Chih Jimmy Chen
Online Machine Learning-based Temperature Prediction for Thermal-aware NoC System. 65-66 - Tae Koan Yoo, Jong Kang Park, Jong Tae Kim:
VLSI Implementation of Area-Efficient Parallelized Neural Network Accelerator Using Hashing Trick. 67-68 - Min-Zhi Ji, Wei-Chung Tseng, Ting-Jia Wu, Bo-Rong Lin, Chung-Ho Chen:
Micro Darknet For Inference: ESL reference for inference accelerator design. 69-70 - Kuan-Chieh Chao
Scalable Multi-DSP Architecture with Clock Adaptation for IoT Access Point. 75-76 - Zelin Meng, Xiangbo Kong, Lin Meng, Hiroyuki Tomiyama:
Lucas-Kanade Optical Flow Based Camera Motion Estimation Approach. 77-78 - Malik Summair Asghar, Saad Arslan, HyungWon Kim, Jaehun Jun, Hyunkyu Park:
Hybrid Concurrent Driving Technique for Large Touch Screen Panels. 79-80 - Shao-I Chu, Yi-Ming Lee, Chen-En Hsieh, Jiun-Han Yen, Yu-Jung Huang:
Stochastic Circuit Design of Image Contrast Stretching. 81-82 - Eunseok Lee, Sujin Park, Nahmil Koo, SeongHwan Cho:
A Low-Power Piezoelectric Speaker Driver Using LC Oscillator for Acoustic Communication. 85-86 - Muhammad Basim, Danial Khan, Khuram Shahzad, Qurat ul Ain, Muhammad Asif, Muhammad Ali, Kang-Yoon Lee:
Design of a High Performance RF Energy Harvester for Wide Input Power Range. 87-88 - Gianfranco Avitabile, Antonello Florio
A Hybrid Hardware Estimation of the Angle of Arrival for Industrial IoT purposes. 89-90 - Herlan Kester Benitez, Christian Haven Cabuso, Maria Theresa G. de Leon, John Richard E. Hizon, Marc D. Rosales:
An SDR-based WSN Testbed for RF Front End Simulation and Experimentation. 91-92 - Phoebe Laine Panis, Maria Sophia Ralota, Joenard Matanguihan, Anastacia B. Alvarez, John Richard E. Hizon, Marc D. Rosales, Christopher Santos, Maria Theresa G. de Leon:
Design and Implementation a Self-starting Thermal Energy Harvester with Resonant Startup and Maximum Power Point Tracking Capabilities/or Wireless Sensor Nodes. 95-96 - Wei-Da Chen, You-Chen Zhang, Hui-Yu Liang:
Implementation of Integrating a High Resolution Time-to-Digital Converter with an Embedded Processor System on Low-Cost FPGA. 97-98 - Tatsuya Maekawa, Yusaku Miwa, Akihito Uno, Daisuke Ito, Makoto Nakamura:
Tunable pre-emphasis architecture for downstream data in long-haul PON systems. 105-106 - Mattis Hasler, Robert Wittig, Emil Matús, Gerhard P. Fettweis:
A Hybrid Execution Approach to Improve the Performance of Dataflow Applications. 107-108 - Wei-Hsuan Ma, Kuan-Ying Chang, Kuan-Ting Chen, Yin-Tsung Hwang, Jin-Fa Lin:
Projection Matching Pursuit based DoA Estimation Scheme and its FPGA Implementation. 109-110 - Eunji Kwon, Yesung Kang, Seokhyeong Kang:
Outlier-aware Time-multiplexing MAC for Higher Energy-Efficiency on CNNs. 119-120 - Sumaiyah I. Khan, Soliman A. Mahmoud
CMOS Subthreshold Balanced Input-Differential Output Four-Quadrant Multiplier for Teager Energy Operator Based Systems. 122-123 - Sanshiro Kimura, Atsuto Imajo, Toshiyuki Inoue
Frequency Discriminator Using a Simple AD Converter for Interface Systems. 128-129 - Tsung-Han Tsai, Ping-Cheng Hao:
Customized Wake-Up Word with Key Word Spotting using Convolutional Neural Network. 136-137 - Yoko Uwate, Yoshifumi Nishio
Nonlinear Time Series Analysis of Coupled Bursting Neuron Model Depending on Coupling Strength. 138-139 - Yoko Uwate, Yoshifumi Nishio
Visualization of Neuron Data using Nonlinear Technic. 142-143 - Kizashi Fukushima, Tadashi Tsubone:
Nonlinear Behavior of Unmanned Aerial Vehicle based on Oscillation Dynamics. 146-147 - Yoshifumi Nishio
Clusteling Methods Using Synchronization of Chaotic Circuit Networks. 152-153 - Kuan-Hung Chen, Jesse Der-Chian Deng, Yin-Tsung Hwang:
A High-Performance Pedestrian Detector and Its Implementation on Embedded Systems for Hypermarket Environment. 154-155 - Chung-Bin Wu
Low Complexity License Plate Recognition System. 156-157 - Tony Tae-Hyoung Kim:
Overview of Memory Design for Next Generation Applications. 162-163 - Cheng-Xin Xue, Meng-Fan Chang:
Challenges in Circuit Designs of Nonvolatile-memory based computing-in-memory for AI Edge Devices. 164-165 - Hyunjoon Kim
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks. 166-167 - JunYoung Kweon, Yun-Heup Song, Tony Tae-Hyoung Kim:
Modelling of Phase Change Memory(PCM) cell for Circuit Simulation. 170-171 - Tso-Bing Juang, Cong-Yi Lin, Guan-Zhong Lin:
Design of High-Speed and Area-Efficient Cartesian to Polar Coordinate Converters Using Logarithmic Number Systems. 180-181 - Zong Jie Shen
Resistive Switching Behavior of Solution-Processed AlOx, based RRAM with Ni and TiN Top Electrode at Low Annealing Temperatures. 182-183 - Sanghyuk Lee, Jaehoon Cha, Kyeong Soo Kim
Data Gathering and Application to Building Energy Optimization with Sensitivity Analysis for IoT Applications. 184-185 - Chana Chansri, Jakkree Srinonchat, Eng Gee Lim
Low Cost Hand Gesture Control in Complex Environment Using Raspberry Pi. 186-187 - Ziqiang Bi
A Novel Global Maximum Power Point Tracking Method based on Shading Detection. 188-189 - Imtinan Basem Attili, Soliman A. Mahmoud
Uncompensated Robust Rail-to-Rail New Amplifier Structure Compatible with Drivers of LCD Panels. 192-193 - Jun Yuan, Xiaobin Tang:
63.2pS at 1.2V dynamic comparator in 65nm CMOS technology. 194-195 - Maha S. Diab
A 6nW Seventh-Order OTA-C Band Pass Filter for Continuous Wavelet Transform. 196-197 - Wan-Ling Wu, Yong-Zheng Wang, Ching-Yuan Yang:
Flipping Rectifiers for Piezoelectric Vibration Energy Harvesting. 198-199 - Yasser Mohammadi Qaragoez
A 5.8GHz 9.5 dBm Class-E Power Amplifier for DSRC Applications. 202-203 - Maha S. Diab
Ultra-Low Power Rectangular Field Programmable Analogue Arrays For Biomedical Applications. 204-205 - Yixuan He, Kyung Ki Kim, Yong-Bin Kim:
Evaluations of Electronic Neuron Model for Low Power VLSI Implementation. 206-207 - Muhammad Faisal, Jawad Yousaf, Wansoo Nah:
Effect of Random Modulation Switching Schemes on Harmonics and CE Levels of a Buck Converter. 208-209 - Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue
Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS. 210-211 - Ahmed Elsiginy, Mohamed Elmahdy, Eman Azab
A Novel Hybrid Analog Design Optimizer with Particle Swarm Optimization and modern Deep Neural Networks. 212-213 - Alec Xavier Manabat, Celine Rose Marcelo, Alfonso Louis Quinquito, Anastacia Alvarez:
Energy-Quality Scalability of Hyperdimensional Computing for Character Recognition in 65nm CMOS. 225-226 - Manikanta Prahlad Manda
Marker-based watershed algorithm for segmentation of the infrared images. 227-228 - Ho-Yun Lee, Yeon-Jin Kim, Do-Yeon Hwang, Jin-Gyun Chung:
Peak Variation Detection Using Variable Length Moving Average Filter for Defects Inspection Systems. 231-232 - Sayali Patil, Young Bae Kim, Haiqing Nan, Li Li, Ken Choi:
Analysis of Performance Variation of Composite Logic in 7nm CMOS Technology Using SBD Effect Based on TDDB. 237-238 - Gyunam Jeon, Kyung Ki Kim, Yong-Bin Kim:
Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation. 241-242 - Olivier Betschi, Ken Choi:
Novel 4-Transistors Ternary Inverter Circuit Using Carbon-Nanotube Field -Effect Transistors. 243-244 - Abdulsami Aldahlawi, Yang-Bin Kim, Kyung Ki Kim:
GPU Architecture Optimization For Mobile Computing. 247-248 - Youngho Seo, Sanghun Lee, Sunwoo Kim, Jooho Wang
Latency-Insensitive Controller for Convolutional Neural Network Accelerators. 249-250 - Pei-Yin Chen, Chi-Huan Tang, Wei-Ting Chen, Hui-Liang Yu:
Dual Path Binary Neural Network. 251-252 - Miyoung Lee, Joohyun Lee, Jinkyu Kim, Byungjo Kim, Juyeob Kim:
The Sparsity and Activation Analysis of Compressed CNN Networks in a HW CNN Accelerator Model. 255-256 - Sandhya Surendarraj, Palagani Yellappa, Jun Rim Choi:
Design of Cardiac Status Indicator and R-R Interval Adjustment Circuits. 257-258 - Lean Karlo S. Tolentino
Development of an IoT-based Aquaponics Monitoring and Correction System with Temperature-Controlled Greenhouse. 261-262 - Wally Enrico M. Ingco
Development of a Spectral Feature Extraction using Enhanced MFCC for Respiratory Sound Analysis. 263-264 - Amrita Rana, Kyung Ki Kim:
ECG Heartbeat Classification Using a Single Layer LSTM Model. 267-268 - Manas Ranjan Meher, Wolfgang Ullmann:
An Innovative I/O Budgeting Methodology for Hierarchical SoC Development. 279-280 - Seong Bin Choi, Sang-Seol Lee, Sung-Joon Jang:
CNN inference simulator for accurate and efficient accelerator design. 283-284 - Jiun Hong, HyungWon Kim, Unsang Yu, Hongju Lee:
Programmable of a Frequency for Concurrent Driving Signals of Touch Screen Controller. 289-290 - Dongil Hwang, Jangseop Shin, Jeehwan Kim, Yunheung Paek:
Data Randomization for Multi-Variant Execution Environment. 291-292 - Seungmin Lee, Bongsoon Kang:
Hardware Implementation of Minimum Filter based on 2-D Cumulative Histogram. 297-298 - Eunchong Lee
An Implementation of the System on Chip Control System for a FPGA-Based Computer Vision Accelerator. 299-300 - Jungah Kim, Shinil Chang, Seungsoo Kim, Hyunchol Shin:
A 1.2 GHz Bandwidth Baseband Analog Circuit in 65nm CMOS for Millimeter-Wave Radio. 301-302 - Miao-Shan Li, Yen-Kuei Lu, Ching-Yuan Yang, Chin-Lung Lin:
PLL-Based Clock and Data Recovery for SSC Embedded Clock Systems. 309-310 - Minho Cheng, Hyunyul Lim, Tae Hyun Kim, Sungho Kang:
A Hardware-efficient TSV Repair Scheme Based on Butterfly Topology. 63-64 - Sangwoo Jung
Noise Tolerance of an Energy-Scalable Deep Learning Model with Two Extreme Bit-Precisions. 71-72 - Kenta Shirane, Takahiro Yamamoto, Ittetsu Taniguchi, Yuko Hara-Azumi, Shigeru Yamashita, Hiroyuki Tomiyama:
Maximum Error-Aware Design of Approximate Array Multipliers. 73-74 - Huo Yingge, Imran Ali, Kang-Yoon Lee:
A Wideband Differential Low Noise Amplifier for TVWS Applications in 130 nm CMOS Technology. 83-84 - Jihye Kim, Sangjun Lee, Minho Moon, Sungho Kang:
Transition-delay Test Methodology for Designs with Self-gating. 93-94 - Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee:
Supporting Serial Interfaces on Virtual SoC Platforms to Develop Sensor Applications. 101-102 - Zhaoqian Zhong, Masato Edahiro:
Model-based Parallelization for Simulink Models on Multicore CPUs and GPUs. 103-104 - Imran Ali, Muhammad Asif, Yasser Mohammadi Qaragoez
An Adaptive PA Modulation Index Controller with Temperature Compensation for DSRC Applications. 111-112 - Seung Chan Lee, Tae Hee Han
A 4-way Matrix Multiply Unit for High Throughput Machine Learning Accelerator. 113-114 - Young-Woo Lee, Youngkwang Lee, Minho Moon, Sungho Kang:
Tunable Compact Probing Detector with Fast Analysis Time Against Invasive Attacks. 115-116 - Fabian Schuiki, Michael Schaffner, Luca Benini:
NTX: A 260 Gflop/sW Streaming Accelerator for Oblivious Floating-Point Algorithms in 22 nm FD-SOI. 117-118 - Daisuke Ito, Tomotaka Tanaka, Makoto Nakamura, Keiji Kishine:
A wideband differential VCO based on double-short-path loop architecture. 126-127 - Jaeseo Park, Yunsoo Lee, Jun Ho Heo, Suk-Ju Kang:
Convolutional Neural Network-based Jaywalking Data Generation and Classification. 132-133 - Kyunghwan Cho, Jihye Kim, Hyunggoy Oh, Sangjun Lee, Sungho Kang:
A New Scan Chain Reordering Method for Low Power Consumption based on Care Bit Density. 134-135 - Liang Chang, Zhaohao Wang, Youguang Zhang, Weisheng Zhao:
Ultra-fast and Energy-efficient Write-Computing Operation for Neuromorphic Computing. 140-141 - Hiroo Sekiya, Yuta Ozawa, Xiuqin Wei:
Load Independent Parallel Resonant Inverter. 148-149 - Shota Uchino, T. Yamamoto, F. Mohamad, K. Shinohara, Tsutomu Iida, Takuji Kousaka, Hirokazu Ohtagaki, Hiroyuki Asahara:
Basic circuit design of high step-up ratio DC-DC converter. 150-151 - Chuen-Yau Chen, Cheng-Yuan Lin, Wei-Ching Liu, Yen-Ting Chen:
Application of Blind-Signal-Processing Algorithm in Image Separation - Blind-Signal-Processing in Image Separation. 158-159 - Duy Thanh Nguyen, Ik-Joon Chang:
Energy-efficient DNN-training with Stretchable DRAM Refresh Controller and Critical-bit Protection. 168-169 - Youngsu Kwon, Yong Cheol Peter Cho, Jeongmin Yang, Jaehoon Chung, Kyoung-Seon Shin, Jinho Han, Chan Kim, Chun-Gi Lyuh, Hyun-Mi Kim, In San Jeon, Min-Seok Choi:
AI 32TFLOPS Autonomous Driving Processor on AI-Ware with Adaptive Power Saving. 174-175 - Julius Ruseckas, Gediminas Molis, Ausra Mackute-Varoneckiene, Tomas Krilavicius
Multi-carrier Signal Detection using Convolutional Neural Networks. 190-191 - Yong Deok Ahn, Su-Jin Oh, Sung-Jin Kim, Kang-Yoon Lee:
A Design of Low Inrush Current Low Dropout Regulator Using the Method of Pre-charging the Load. 214-215 - Erwin Setiawan, Trio Adiono:
Throughput Improvement of an Autocorrelation Block for Time Synchronization in OFDM-based LiFi. 219-220 - Cheol-Won Jo, Kwang-Yeob Lee:
Design of multicycle path accelerator for neural network. 221-224 - Muhammad Asif, Imran Ali, Yasser Mohammadi Qaragoez
A Configurable Linear PA Ramp Controller for DSRC Applications in 130 nm CMOS Technology. 229-230 - Muhammad Riaz ur Rehman, Imran Ali, Pervesh Kumar
Real time High Accuracy Phase Difference Measurement for Parallel Multi-Channel Sensors. 233-234 - Hayoung Lee
Redundancy Analysis based on Fault Distribution for Memory with Complex Spares. 235-236 - Hoyoung Yu, Hyung-Min Lee
FPGA reverse engineering in Vivado design suite based on X-ray project. 239-240 - Seonyoung Lee, Haengson Son, Yunjeong Kim, Kyoungwon Min:
Design of hand skeleton extraction accelerator for a real-time hand gesture recognition. 245-246 - Yun-Nan Chang, Yu-Tang Tin:
Scaling Bit-Flexible Neural Networks. 253-254 - Chaeun Lee, Jaehyun Kim, Kiyoung Choi:
An RRAM-based Analog Neuron Design for the Weighted Spiking Neural network. 259-260 - Young Hyun Yoon, Su-Yeon Jang
Flexible Embedded AI System with High-speed Neuromorphic Controller. 265-266
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