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42nd ISCA 2015: Portland, OR, USA
- Deborah T. Marr, David H. Albonesi:
Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, OR, USA, June 13-17, 2015. ACM 2015, ISBN 978-1-4503-3402-0
Datacenter architectures I
- Sang Woo Jun
, Ming Liu, Sungjin Lee, Jamey Hicks, John Ankcorn, Myron King, Shuotao Xu, Arvind:
BlueDBM: an appliance for big data analytics. 1-13 - Chao Li, Yang Hu, Longjun Liu
Towards sustainable in-situ server systems in the big data era. 14-26 - Johann Hauswald, Yiping Kang, Michael A. Laurenzano, Quan Chen, Cheng Li, Trevor N. Mudge, Ronald G. Dreslinski, Jason Mars, Lingjia Tang:
DjiNN and Tonic: DNN as a service and its implications for future warehouse scale computers. 27-40
GPUs I
- Nandita Vijaykumar, Gennady Pekhimenko, Adwait Jog, Abhishek Bhowmick, Rachata Ausavarungnirun, Chita R. Das, Mahmut T. Kandemir, Todd C. Mowry, Onur Mutlu:
A case for core-assisted bottleneck acceleration in GPUs: enabling flexible data compression with assist warps. 41-53 - Indrani Paul
Harmonia: balancing compute and memory power in high-performance GPUs. 54-65
Virtual memory management
- Vasileios Karakostas, Jayneel Gandhi
Redundant memory mappings for fast access to large memories. 66-78 - Vivek Seshadri, Gennady Pekhimenko, Olatunji Ruwase, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry, Trishul M. Chilimbi:
Page overlays: an enhanced virtual memory framework to enable fine-grained memory management. 79-91
Accelerators I
- Zidong Du, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Xiaobing Feng, Yunji Chen
ShiDianNao: shifting vision processing closer to the sensor. 92-104 - Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi:
A scalable processing-in-memory accelerator for parallel graph processing. 105-117 - Chen-Han Ho, Sung Jin Kim, Karthikeyan Sankaralingam:
Efficient execution of memory access phases using dataflow specialization. 118-130 - Berkin Akin, Franz Franchetti, James C. Hoe:
Data reorganization in memory using 3D-stacked DRAM. 131-143
Performance analysis and tools
- Takuya Nakaike, Rei Odaira, Matthew Gaudet, Maged M. Michael, Hisanobu Tomari:
Quantitative comparison of hardware transactional memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8. 144-157 - Svilen Kanev, Juan Pablo Darago, Kim M. Hazelwood, Parthasarathy Ranganathan, Tipp Moseley, Gu-Yeon Wei, David M. Brooks:
Profiling a warehouse-scale computer. 158-169 - Xi Yang, Stephen M. Blackburn
Computer performance microscopy with Shim. 170-184 - Mark Stephenson, Siva Kumar Sastry Hari, Yunsup Lee, Eiman Ebrahimi, Daniel R. Johnson, David W. Nellans, Mike O'Connor
Flexible software profiling of GPU architectures. 185-197
DRAM caches and architectures
- Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches. 198-210 - Yongjun Lee, Jongwon Kim, Hakbeom Jang, Hyunggyun Yang, Jangwoo Kim, Jinkyu Jeong
A fully associative, tagless DRAM cache. 211-222 - Jungwhan Choi, Wongyu Shin, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Lee-Sup Kim:
Multiple clone row DRAM: a low latency and area optimized DRAM. 223-234 - Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob:
Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions. 235-246
Processor architecture I
- Arthur Perais
Cost-effective speculative scheduling in high performance processors. 247-259 - Görkem Asilioglu, Zhaoxiang Jin, Murat Köksal, Omkar Javeri, Soner Önder:
LaZy superscalar. 260-271 - Trevor E. Carlson
The load slice core microarchitecture. 272-284 - Leeor Peled
Semantic locality and context-based prefetching using reinforcement learning. 285-297
Processor architecture II
- Tony Nowatzki, Vinay Gangadhar, Karthikeyan Sankaralingam:
Exploring the potential of heterogeneous von neumann/dataflow execution models. 298-310 - Bruno Cardoso Lopes, Rafael Auler, Luiz Ramos, Edson Borin, Rodolfo Azevedo
SHRINK: reducing the ISA complexity via instruction recycling. 311-322 - Daniel S. McFarlin, Craig B. Zilles:
Branch vanguard: decomposing branch functionality into prediction and resolution instructions. 323-335
Memory systems I
- Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi:
PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture. 336-348 - Subhasis Das, Tor M. Aamodt, William J. Dally:
SLIP: reducing wire energy in the memory hierarchy. 349-361
Security and virtualization
- Tianwei Zhang, Ruby B. Lee:
CloudMonatt: an architecture for security health monitoring and attestation of virtual machines in cloud computing. 362-374 - Wenhao Li, Yubin Xia, Haibo Chen, Binyu Zang, Haibing Guan:
Reducing world switches in virtualized environment with flexible cross-world calls. 375-387
Parallel architectures
- Daniel Lustig, Caroline Trippel, Michael Pellauer, Margaret Martonosi:
ArMOR: defending against memory consistency model mismatches in heterogeneous architectures. 388-400 - Cedomir Segulja, Tarek S. Abdelrahman:
Clean: a race detector with cleaner semantics. 401-413 - Ching-Kai Liang, Milos Prvulovic:
MiSAR: minimalistic synchronization accelerator with resource overflow management. 414-426 - Alberto Ros
Callback: efficient synchronization without invalidation with a directory just for spin-waiting. 427-438
Datacenter architectures II
- Matt Skach, Manish Arora, Chang-Hong Hsu, Qi Li, Dean M. Tullsen
Thermal time shifting: leveraging phase change materials to reduce cooling costs in warehouse-scale computers. 439-449 - David Lo, Liqun Cheng, Rama Govindaraju, Parthasarathy Ranganathan, Christos Kozyrakis:
Heracles: improving resource efficiency at scale. 450-462 - Longjun Liu
HEB: deploying and managing hybrid energy buffers for improving datacenter efficiency and economy. 463-475 - Sheng Li, Hyeontaek Lim, Victor W. Lee, Jung Ho Ahn
Architecting to achieve a billion requests per second throughput on a single key-value store server platform. 476-488
GPUs II
- Timothy G. Rogers
A variable warp size architecture. 489-501 - Sangpil Lee, Keunsoo Kim, Gunjae Koo
Warped-compression: enabling power efficient GPUs through register compression. 502-514 - Shin-Ying Lee, Akhil Arunkumar, Carole-Jean Wu:
CAWA: coordinated warp scheduling and cache prioritization for critical warp acceleration of GPGPU workloads. 515-527 - Jin Wang, Norm Rubin, Albert Sidelnik, Sudhakar Yalamanchili:
Dynamic thread block launch: a lightweight execution mechanism to support irregular applications on GPUs. 528-540
Accelerators II
- Feng Liu, Heejin Ahn, Stephen R. Beard, Taewook Oh, David I. August:
DynaSpAM: dynamic spatial architecture mapping using out of order instruction schedules. 541-553 - Daya Shanker Khudia, Babak Zamirai, Mehrzad Samadi, Scott A. Mahlke:
Rumba: an online quality management system for approximate computing. 554-566
Networks and storage
- Alexandros Daglis, Stanko Novakovic, Edouard Bugnion, Babak Falsafi, Boris Grot
Manycore network interfaces for in-memory rack-scale computing. 567-579 - Jian Huang, Anirudh Badam, Moinuddin K. Qureshi, Karsten Schwan:
Unified address translation for memory-mapped SSDs with FlashMap. 580-591
Security
- Robert Locke Callan, Alenka G. Zajic, Milos Prvulovic:
FASE: finding amplitude-modulated side-channel emanations. 592-603 - Amir Rahmati
Probable cause: the deanonymizing effects of approximate DRAM. 604-615 - Xiangyao Yu, Syed Kamran Haider, Ling Ren, Christopher W. Fletcher, Albert Kwon, Marten van Dijk
PrORAM: dynamic prefetcher for oblivious RAM. 616-628
Mobile and embedded systems
- Pat Pannuto
MBus: an ultra-low power interconnect bus for next generation nanopower systems. 629-641 - Gaurav Chadha, Scott A. Mahlke, Satish Narayanasamy
Accelerating asynchronous programs through event sneak peek. 642-654 - Nachiappan Chidambaram Nachiappan
VIP: virtualizing IP chains on handheld platforms. 655-667
Dependable architectures
- Nitin, Irith Pomeranz, T. N. Vijaykumar:
FaultHound: value-locality-based soft-fault tolerance. 668-681 - David J. Palframan, Nam Sung Kim, Mikko H. Lipasti:
COP: to compress and protect main memory. 682-693 - Chao Zhang, Guangyu Sun, Xian Zhang, Weiqi Zhang, Weisheng Zhao, Tao Wang, Yun Liang, Yongpan Liu, Yu Wang, Jiwu Shu:
Hi-fi playback: tolerating position errors in shift operations of racetrack memory. 694-706
Memory systems II
- Rakesh Komuravelli, Matthew D. Sinclair, Johnathan Alsop, Muhammad Huzaifa, Maria Kotsifakou, Prakalp Srivastava, Sarita V. Adve, Vikram S. Adve:
Stash: have your scratchpad and cache it too. 707-719 - Lluc Alvarez
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures. 720-732 - Snehasish Kumar, Arrvindh Shriraman, Naveen Vedula:
Fusion: design tradeoffs in coherent cache hierarchies for accelerators. 733-745
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