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MBus: an ultra-low power interconnect bus for next generation nanopower systems

Authors:

Benjamin Kempke,

Ronald G. Dreslinski,

Prabal DuttaAuthors Info & Claims

ISCA '15: Proceedings of the 42nd Annual International Symposium on Computer Architecture

Pages 629 - 641

https://doi.org/10.1145/2749469.2750376

Published: 13 June 2015 Publication History

Abstract

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized---yet reusable---components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead.

We present MBus, a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts.

To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2mm³ MBus system draws 8nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus's feature set.

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Index Terms

MBus: an ultra-low power interconnect bus for next generation nanopower systems
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Interconnect

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cover image ACM Conferences

ISCA '15: Proceedings of the 42nd Annual International Symposium on Computer Architecture

June 2015

768 pages

ISBN:9781450334020

DOI:10.1145/2749469

General Chair:
Debbie Marr
Intel
,
Program Chair:
David Albonesi
Cornell

ACM SIGARCH Computer Architecture News Volume 43, Issue 3S
ISCA'15
June 2015
745 pages
ISSN:0163-5964
DOI:10.1145/2872887
Editor:
Doug DeGroot
acm dot org
Issue’s Table of Contents

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Published: 13 June 2015

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ISCA '15: The 42nd Annual International Symposium on Computer Architecture

June 13 - 17, 2015

Oregon, Portland

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

Lee IHsiao RCarichner GHsu CYang MShoouri SErnst KCarichner TLi YLim JJulick CMoon ESun YPhillips JMontooth KGreen II DKim HBlaauw D(2024)mSAIL: Milligram-Scale Multi-modal Sensor Platform for Monarch Butterfly Migration TrackingCommunications of the ACM10.1145/3611105(1-9)Online publication date: 12-Apr-2024
https://doi.org/10.1145/3611105
Li YKim YLee I(2023) A 5-mm 2 , 4.7- μ W Convolutional Neural Network Layer Accelerator for Miniature Systems IEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.332457231:12(2142-2146)Online publication date: Dec-2023
https://doi.org/10.1109/TVLSI.2023.3324572
Li YWu YZhang XHu JLee I(2022)Energy-Aware Adaptive Multi-Exit Neural Network Inference Implementation for a Millimeter-Scale Sensing SystemIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.317130830:7(849-859)Online publication date: Jul-2022
https://doi.org/10.1109/TVLSI.2022.3171308
Lee IHsiao RCarichner GHsu CYang MShoouri SErnst KCarichner TLi YLim JJulick CMoon ESun YPhillips JMontooth KGreen DKim HBlaauw D(2021)mSAILProceedings of the 27th Annual International Conference on Mobile Computing and Networking10.1145/3447993.3483263(517-530)Online publication date: 25-Oct-2021
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Lee JKim YCho MYasuda MMiyoshi SKawaminami MBlaauw DSylvester D(2020)A$\mu$Processor Layer for mm-Scale Die-Stacked Sensing Platforms Featuring Ultra-Low Power Sleep Mode at 125°C2020 IEEE Asian Solid-State Circuits Conference (A-SSCC)10.1109/A-SSCC48613.2020.9336116(1-4)Online publication date: 9-Nov-2020
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Oh SCho MWu XKim YChuo LLim WPannuto PBang SYang KKim HSylvester DBlaauw D(2019) IoT 2 — the Internet of Tiny Things: Realizing mm-Scale Sensors through 3D Die Stacking 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715201(686-691)Online publication date: Mar-2019
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