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Daniel Lustig
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- affiliation: Nvidia Corporation, USA
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2020 – today
- 2023
- [c22]Vijay Kandiah, Daniel Lustig, Oreste Villa, David W. Nellans, Nikos Hardavellas
:
Parsimony: Enabling SIMD/Vector Programming in Standard Compiler Flows. CGO 2023: 186-198 - [c21]Harini Muthukrishnan, Daniel Lustig, Oreste Villa, Thomas F. Wenisch, David W. Nellans:
FinePack: Transparently Improving the Efficiency of Fine-Grained Transfers in Multi-GPU Systems. HPCA 2023: 516-529 - 2022
- [c20]Daniel Lustig, Simon Cooksey, Olivier Giroux:
Mixed-proxy extensions for the NVIDIA PTX memory consistency model: industrial product. ISCA 2022: 1058-1070 - 2021
- [c19]Oreste Villa, Daniel Lustig, Zi Yan
Need for Speed: Experiences Building a Trustworthy System-Level GPU Simulator. HPCA 2021: 868-880 - [c18]Harini Muthukrishnan, David W. Nellans, Daniel Lustig, Jeffrey A. Fessler, Thomas F. Wenisch:
Efficient Multi-GPU Shared Memory via Automatic Optimization of Fine-Grained Transfers. ISCA 2021: 139-152 - [c17]Harini Muthukrishnan, Daniel Lustig, David W. Nellans, Thomas F. Wenisch:
GPS: A Global Publish-Subscribe Model for Multi-GPU Memory Management. MICRO 2021: 46-58 - 2020
- [c16]Xiaowei Ren, Daniel Lustig, Evgeny Bolotin, Aamer Jaleel, Oreste Villa, David W. Nellans:
HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems. HPCA 2020: 582-595 - [i5]Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi:
RealityCheck: Bringing Modularity, Hierarchy, and Abstraction to Automated Microarchitectural Memory Consistency Verification. CoRR abs/2003.04892 (2020)
2010 – 2019
- 2019
- [j7]Caroline Trippel
Security Verification via Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach. IEEE Micro 39(3): 84-93 (2019) - [c15]Daniel Lustig, Sameer Sahasrabuddhe, Olivier Giroux:
A Formal Analysis of the NVIDIA PTX Memory Consistency Model. ASPLOS 2019: 257-270 - [c14]Zi Yan
Nimble Page Management for Tiered Memory Systems. ASPLOS 2019: 331-345 - [c13]Zi Yan
Translation ranger: operating system support for contiguity-aware TLBs. ISCA 2019: 698-710 - 2018
- [j6]Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi:
Full-Stack Memory Model Verification with TriCheck. IEEE Micro 38(3): 58-68 (2018) - [c12]Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Aarti Gupta
PipeProof: Automated Memory Consistency Proofs for Microarchitectural Specifications. MICRO 2018: 788-801 - [c11]Caroline Trippel, Daniel Lustig, Margaret Martonosi:
CheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests. MICRO 2018: 947-960 - [i4]Caroline Trippel, Daniel Lustig, Margaret Martonosi:
MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence Protocols. CoRR abs/1802.03802 (2018) - 2017
- [b2]Abhishek Bhattacharjee, Daniel Lustig:
Architectural and Operating System Support for Virtual Memory. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2017, ISBN 978-3-031-00629-6 - [j5]Daniel Lustig, Geet Sethi, Abhishek Bhattacharjee, Margaret Martonosi:
Transistency Models: Memory Ordering at the Hardware-OS Interface. IEEE Micro 37(3): 88-97 (2017) - [c10]Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi:
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA. ASPLOS 2017: 119-133 - [c9]Daniel Lustig, Andrew Wright, Alexandros Papakonstantinou, Olivier Giroux:
Automated Synthesis of Comprehensive Memory Model Litmus Test Suites. ASPLOS 2017: 661-675 - [c8]Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer:
RTLcheck: verifying the memory consistency of RTL designs. MICRO 2017: 463-476 - [i3]Sizhuo Zhang, Muralidaran Vijayaraghavan, Dan Lustig, Arvind:
Weak Memory Models with Matching Axiomatic and Operational Definitions. CoRR abs/1710.04259 (2017) - 2016
- [c7]Daniel Lustig, Geet Sethi, Margaret Martonosi, Abhishek Bhattacharjee
COATCheck: Verifying Memory Ordering at the Hardware-OS Interface. ASPLOS 2016: 233-247 - [i2]Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi:
Exploring the Trisection of Software, Hardware, and ISA in Memory Model Design. CoRR abs/1608.07547 (2016) - [i1]Yatin A. Manerkar, Caroline Trippel, Daniel Lustig, Michael Pellauer, Margaret Martonosi:
Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings. CoRR abs/1611.01507 (2016) - 2015
- [b1]Daniel Lustig:
Specifying, Verifying, and Translating Between Memory Consistency Models. Princeton University, USA, 2015 - [j4]Daniel Lustig, Michael Pellauer, Margaret Martonosi:
Verifying Correct Microarchitectural Enforcement of Memory Consistency Models. IEEE Micro 35(3): 72-82 (2015) - [j3]Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer:
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. ACM Trans. Comput. Syst. 33(3): 10:1-10:32 (2015) - [c6]Daniel Lustig, Caroline Trippel, Michael Pellauer, Margaret Martonosi:
ArMOR: defending against memory consistency model mismatches in heterogeneous architectures. ISCA 2015: 388-400 - [c5]Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi:
CCICheck: using µhb graphs to verify the coherence-consistency interface. MICRO 2015: 26-37 - 2014
- [j2]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Efficient Spatial Processing Element Control via Triggered Instructions. IEEE Micro 34(3): 120-137 (2014) - [c4]Daniel Lustig, Michael Pellauer, Margaret Martonosi:
Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models. MICRO 2014: 635-646 - 2013
- [j1]Daniel Lustig, Abhishek Bhattacharjee, Margaret Martonosi:
TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs. ACM Trans. Archit. Code Optim. 10(1): 2:1-2:38 (2013) - [c3]Daniel Lustig, Margaret Martonosi:
Reducing GPU offload latency via fine-grained CPU-GPU synchronization. HPCA 2013: 354-365 - [c2]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Triggered instructions: a control paradigm for spatially-programmed architectures. ISCA 2013: 142-153 - 2011
- [c1]Abhishek Bhattacharjee, Daniel Lustig, Margaret Martonosi:
Shared last-level TLBs for chip multiprocessors. HPCA 2011: 62-63
Coauthor Index
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