research-article

ArMOR: defending against memory consistency model mismatches in heterogeneous architectures

Authors:

Caroline Trippel,

Michael Pellauer,

Margaret MartonosiAuthors Info & Claims

ISCA '15: Proceedings of the 42nd Annual International Symposium on Computer Architecture

Pages 388 - 400

https://doi.org/10.1145/2749469.2750378

Published: 13 June 2015 Publication History

Abstract

Architectural heterogeneity is increasing: numerous products and studies have proven the benefits of combining cores and accelerators with varying ISAs into a single system. However, an underappreciated barrier to unlocking the full potential of heterogeneity is the need to specify and to reconcile differences in memory consistency models across layers of the hardware-software stack and among on-chip components.

This paper presents ArMOR, a framework for specifying, comparing, and translating between memory consistency models. ArMOR defines MOSTs, an architecture-independent and precise format for specifying the semantics of memory ordering requirements such as preserved program order or explicit fences. MOSTs allow any two consistency models to be directly and algorithmically compared, and they help avoid many of the pitfalls of traditional consistency model analysis. As a case study, we use ArMOR to automatically generate translation modules called shims that dynamically translate code compiled for one memory model to execute on hardware implementing a different model.

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Cited By

Zhang AGoens AOswald NGrosser TSorin DNagarajan V(2024)PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency ModelProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676889(1-13)Online publication date: 14-Oct-2024
https://dl.acm.org/doi/10.1145/3656019.3676889
Beck MBhat KStričević LChen GBehrens DFu MVafeiadis VChen HHärtig HAamodt TJerger NSwift M(2023)AtoMig: Automatically Migrating Millions Lines of Code from TSO to WMMProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3575693.3579849(61-73)Online publication date: 27-Jan-2023
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Gouicem RSprokholt DRuehl JRocha RSpink TChakraborty SBhatotia PAamodt TJerger NSwift M(2023)Risotto: A Dynamic Binary Translator for Weak Memory Model ArchitecturesProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 110.1145/3567955.3567962(107-122)Online publication date: 25-Mar-2023
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Index Terms

ArMOR: defending against memory consistency model mismatches in heterogeneous architectures
1. Computer systems organization
  1. Architectures
2. Hardware

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cover image ACM Conferences

ISCA '15: Proceedings of the 42nd Annual International Symposium on Computer Architecture

June 2015

768 pages

ISBN:9781450334020

DOI:10.1145/2749469

General Chair:
Debbie Marr
Intel
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Program Chair:
David Albonesi
Cornell

ACM SIGARCH Computer Architecture News Volume 43, Issue 3S
ISCA'15
June 2015
745 pages
ISSN:0163-5964
DOI:10.1145/2872887
Editor:
Doug DeGroot
acm dot org
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Published: 13 June 2015

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Cited By

Zhang AGoens AOswald NGrosser TSorin DNagarajan V(2024)PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency ModelProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676889(1-13)Online publication date: 14-Oct-2024
https://dl.acm.org/doi/10.1145/3656019.3676889
Beck MBhat KStričević LChen GBehrens DFu MVafeiadis VChen HHärtig HAamodt TJerger NSwift M(2023)AtoMig: Automatically Migrating Millions Lines of Code from TSO to WMMProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3575693.3579849(61-73)Online publication date: 27-Jan-2023
https://dl.acm.org/doi/10.1145/3575693.3579849
Gouicem RSprokholt DRuehl JRocha RSpink TChakraborty SBhatotia PAamodt TJerger NSwift M(2023)Risotto: A Dynamic Binary Translator for Weak Memory Model ArchitecturesProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 110.1145/3567955.3567962(107-122)Online publication date: 25-Mar-2023
https://dl.acm.org/doi/10.1145/3567955.3567962
Oswald NNagarajan VSorin DGavrielatos VOlausson TCarr R(2023)HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence ProtocolsIEEE Micro10.1109/MM.2023.327499343:4(62-70)Online publication date: 1-Jul-2023
https://dl.acm.org/doi/10.1109/MM.2023.3274993
Zeng XZhang S(2023)Parallelizing Stream Compression for IoT Applications on Asymmetric Multicores2023 IEEE 39th International Conference on Data Engineering (ICDE)10.1109/ICDE55515.2023.00078(950-964)Online publication date: Apr-2023
https://doi.org/10.1109/ICDE55515.2023.00078
Rocha RSprokholt DFink MGouicem RSpink TChakraborty SBhatotia PJhala RDillig I(2022)Lasagne: a static binary translator for weak memory model architecturesProceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation10.1145/3519939.3523719(888-902)Online publication date: 9-Jun-2022
https://dl.acm.org/doi/10.1145/3519939.3523719
Oswald NNagarajan VSorin DGavrielatos VOlausson TCarr R(2022)HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00061(756-771)Online publication date: Apr-2022
https://doi.org/10.1109/HPCA53966.2022.00061
Nagarajan VSorin DHill MWood DNagarajan VSorin DHill MWood D(2022)Consistency and Coherence for Heterogeneous SystemsA Primer on Memory Consistency and Cache Coherence10.1007/978-3-031-01764-3_10(211-251)Online publication date: 28-Mar-2022
https://doi.org/10.1007/978-3-031-01764-3_10
Nagarajan VSorin DHill MWood D(2020)A Primer on Memory Consistency and Cache Coherence, Second EditionSynthesis Lectures on Computer Architecture10.2200/S00962ED2V01Y201910CAC04915:1(1-294)Online publication date: 4-Feb-2020
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Zhao ZJiang ZLiu XGong XWang WYew P(2020)DQEMU: A Scalable Emulator with Retargetable DBT on Distributed PlatformsProceedings of the 49th International Conference on Parallel Processing10.1145/3404397.3404403(1-11)Online publication date: 17-Aug-2020
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