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18. ACM Great Lakes Symposium on VLSI 2008: Orlando, Florida, USA
- Vijaykrishnan Narayanan, Zhiyuan Yan, Enrico Macii, Sanjukta Bhanja:
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008. ACM 2008, ISBN 978-1-59593-999-9
Tutorials
- Syed M. Alam, Mike Ignatowski, Yuan Xie:
Technology, CAD tools, and designs for emerging 3D integration technology. 1-2
Plenary talk 1
- Tak H. Ning:
GLSVLSI 2008 invited/keynote talk. 3-4
Session 1A: Modeling and Design under Variations
- Andrea Calimera
, Enrico Macii, Massimo Poncino, R. Iris Bahar
Temperature-insensitive synthesis using multi-vt libraries. 5-10 - Min-Chun Tsai:
A formula of STI cmp design rule. 11-16 - Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl:
Considering possible opens in non-tree topology wire delay calculation. 17-22 - Jian Cui, Gengsheng Chen, Ruijing Shen, Sheldon X.-D. Tan, Wenjian Yu, Jiarong Tong:
Variational capacitance modeling using orthogonal polynomial method. 23-28
Session 1B: Addressing Emerging Technology Issues in VLSI Circuits
- Hamed Abrishami, Safar Hatami, Behnam Amelifard, Massoud Pedram:
NBTI-aware flip-flop characterization and design. 29-34 - Matthew Seetharam A. Holtz, Seetharam Narasimhan, Swarup Bhunia
On-die CMOS voltage droop detection and dynamiccompensation. 35-40 - Basab Datta, Wayne P. Burleson:
Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators. 41-46 - Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos:
A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip. 47-52
Session 2A: Cryptography and Architecture
- Santosh Ghosh, Monjur Alam, Dipanwita Roy Chowdhury, Indranil Sengupta:
A GF(p) elliptic curve group operator resistant against side channel attacks. 53-58 - Ambrose Chu, Scott Miller, Mihai Sima:
Reconfigurable solutions for very-long arithmetic with applications in cryptography. 59-64 - Renfei Liu, Keshab K. Parhi
Fast composite field S-box architectures for advanced encryption standard. 65-70 - Pablo Viana, Ann Gordon-Ross, Edna Barros
A table-based method for single-pass cache optimization. 71-76
Session 2B: System-Level Testing, Verification and Design
- André Sülflow, Görschwin Fey
Using unsatisfiable cores to debug multiple design errors. 77-82 - Kanad Basu, Prabhat Mishra
A novel test-data compression technique using application-aware bitmask and dictionary selection methods. 83-88 - Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto:
HyMacs: hybrid memory access optimization based on custom-instruction scheduling. 89-94 - Youngsik Kim, Nazanin Mansouri:
Automated formal verification of scheduling with speculative code motions. 95-100 - Safar Hatami, Hamed Abrishami, Massoud Pedram:
Statistical timing analysis of flip-flops considering codependent setup and hold times. 101-106
Poster session 1
- Ivan D. Castellanos, James E. Stine
Compressor trees for decimal partial product reduction. 107-110 - J. V. R. Ravindra, M. B. Srinivas:
Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits. 111-114 - Dimitris Bekiaris, Kiamal Z. Pekmestzi, Christos A. Papachristou
A high-speed radix-4 multiplexer-based array multiplier. 115-118 - Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri:
A robust, fast pulsed flip-flop design. 119-122 - Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
A low leakage 9t sram cell for ultra-low power operation. 123-126 - Yarallah Koolivand, Seyed Morteza Alavi, Omid Shoaei
New technique in design of active rf cmos mixers for low flicker noise and high conversion gain. 127-130 - Greg Stitt, Jason R. Villarreal:
Recursion flattening. 131-134 - Mu-Shun Matt Lee, Chin-Hsun Lin, Chien-Nan Jimmy Liu, Shih-Che Lin:
Quick supply current waveform estimation at gate level using existed cell library information. 135-138 - Mingsong Chen, Prabhat Mishra
Coverage-driven automatic test generation for uml activity diagrams. 139-142 - Greg Stitt:
Hardware/software partitioning with multi-version implementation exploration. 143-146 - Kanupriya Gulati, Sunil P. Khatri:
Improving FPGA routability using network coding. 147-150 - Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud:
Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology. 151-154 - Meikang Qiu, Jiande Wu:
Energy saving for memory with loop scheduling and prefetching. 155-158 - Almitra Pradhan, Ranga Vemuri
A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection. 159-162 - Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
Delay driven AIG restructuring using slack budget management. 163-166 - Andrey Ayupov, Alexander Marchenko, Vladimir Tiourin:
An analytical approach to placement legalization. 167-170
Session 3A: Low Power Circuits
- N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam:
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. 171-176 - Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini
Optimal sleep transistor synthesis under timing and area constraints. 177-182 - Karthik Duraisami, Enrico Macii, Massimo Poncino:
Energy efficiency bounds of pulse-encoded buses. 183-188 - Raghid Shreih, Maitham Shams:
Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies. 189-194
Session 3B: Modeling and Design of Advanced VLSI Circuits
- Hamid Nejati, Tamer Ragheb, Yehia Massoud:
On the design of customizable low-voltage common-gate LNA-mixer pair using current and charge reusing techniques. 195-200 - Mark R. Greenstreet, Suwen Yang:
Verifying start-up conditions for a ring oscillator. 201-206 - Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto:
A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm. 207-212 - Suganth Paul, Rajesh Garg, Sunil P. Khatri:
Pipelined network of PLA based circuit design. 213-218 - Chanyang Joo, Soojae Kim, Kwangsub Yoon:
A low-power 12-bit 80MHz CMOS DAC using pseudo-segmentation. 219-222
Plenary talk 2: "Architectures for Distributed Smart Cameras"
- Wayne H. Wolf:
GLSVLSI 2008 invited/keynote talk. 223-224
Session 4A: Emerging Technologies
- Yexin Zheng, Michael S. Hsiao, Chao Huang:
SAT-based equivalence checking of threshold logic designs for nanotechnologies. 225-230 - Nathan O. Scott, Gerhard W. Dueck:
Pairwise decomposition of toffoli gates in a quantum circuit. 231-236 - Vamsi Vankamamidi, Fabrizio Lombardi:
Design of defect tolerant tile-based QCA circuits. 237-242 - Mayur Bubna, Sudip Roy, Naresh Shenoy, Subhra Mazumdar:
A layout-aware physical design method for constructing feasible QCA circuits. 243-248 - Harika Manem, Peter C. Paliwoda, Garrett S. Rose
A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays. 249-254
Session 4B: Physical synthesis
- Liangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong:
A novel performance driven power gating based on distributed sleep transistor network. 255-260 - Nikolai Ryzhenko, Oleg Venger:
A practical repeater insertion flow. 261-266 - Hao Li, Yue Zhuo:
Criticality history guided FPGA placement algorithm for timing optimization. 267-272 - Koustav Bhattacharya, Nagarajan Ranganathan:
A linear programming formulation for security-aware gate sizing. 273-278
Session 5A: Testing and Resilient Circuits
- Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan:
On efficient generation of instruction sequences to test for delay defects in a processor. 279-284 - Zhenyu Qi, Mircea R. Stan
NBTI resilient circuits using adaptive body biasing. 285-290 - Jin Guo, Antonis Papanikolaou, Michele Stucchi, Kristof Croes, Zsolt Tokei, Francky Catthoor:
A tool flow for predicting system level timing failures due to interconnect reliability degradation. 291-296 - Drew C. Ness, David J. Lilja:
Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages. 297-302 - Md. Sajjad Rahaman, Masud H. Chowdhury:
Improved ber performance in intra-chip rf/wireless interconnect systems. 303-308
Session 5B: VLSI Design
- Xianfang Tan, Lei Zhang, Shankar Neelkrishnan, Mei Yang, Yingtao Jiang, Yulu Yang:
Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology. 309-314 - Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng:
A lithography-friendly structured ASIC design approach. 315-320 - Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez:
Efficient tree topology for FPGA interconnect network. 321-326 - Charbel J. Akl, Magdy A. Bayoumi:
Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count. 327-332 - Ernesto Ordoñez-Cardenas, René de Jesús Romero-Troncoso:
Mlp neural network and on-line backpropagation learning implementation in a low-cost fpga. 333-338
Poster session 2
- Jingye Xu, Pervez Khaled, Masud H. Chowdhury:
Fast bus waveform estimation at the presence of coupling noise. 339-342 - Santanu Kundu, Santanu Chattopadhyay
Mesh-of-tree deterministic routing for network-on-chip architecture. 343-346 - Yufeng Lu, Erdal Oruklu, Jafar Saniie:
Fpga-based hardware/software co-design for chirplet signal decomposition. 347-350 - Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones:
Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip. 351-354 - Richard Putman:
Using reiterative LFSR based X-masking to increase output compression in presence of unknowns. 355-358 - Lun-Chun Wei, Hung-Ming Chen, Li-Da Huang, Sarah Songjie Xu:
Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow. 359-362 - Mainak Banga, Maheshwar Chandrasekar, Lei Fang, Michael S. Hsiao:
Guided test generation for isolation and detection of embedded trojans in ics. 363-366 - Mark M. Budnik, Eric W. Johnson, Joshua D. Wood:
Electrical models for vertical carbon nanotube capacitors. 367-370 - Kimish Patel, Wonbok Lee, Massoud Pedram:
In-order pulsed charge recycling in off-chip data buses. 371-374 - Andrea Acquaviva, Franco Fummi, Giovanni Perbellini, Davide Quaglia
An energy-aware co-simulation framework for the design of wireless sensor networks. 375-378 - Ann Gordon-Ross, Jeremy Lau, Brad Calder:
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy. 379-382 - Maziar Goudarzi
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. 383-386 - Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. 387-390 - Shaobo Liu, Qinru Qiu, Qing Wu:
Full-chip leakage current estimation based on statistical sampling techniques. 391-394 - Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim:
A low-power phase change memory based hybrid cache architecture. 395-398 - Yen-Jen Chang:
Exploiting frequent opcode locality for power efficient instruction cache. 399-402 - Tadayuki Matsumura, Tohru Ishihara
Simultaneous optimization of memory configuration and code allocation for low power embedded systems. 403-406 - Paulo F. Butzen
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. 407-410
Session 6A: Low Power Architecture
- Pu Liu, Sheldon X.-D. Tan, Wei Wu, Murli Tirumala:
FEKIS: a fast architecture-level thermal analyzer for online thermal regulation. 411-416 - Shervin Sharifi, Tajana Simunic Rosing:
An analytical model for the upper bound on temperature differences on a chip. 417-422 - Abu Saad Papa, Madhu Mutyam
Power management of variation aware chip multiprocessors. 423-428 - Venkatesh Arunachalam, Wayne P. Burleson:
Low-power clock distribution in a multilayer core 3d microprocessor. 429-434 - Cesare Ferri, Amber Viescas, Tali Moreshet, R. Iris Bahar
Energy efficient synchronization techniques for embedded architectures. 435-440
Session 6B: ADC and LDPC
- Jaeyong Lee, Sungil Cho, Kwangsub Yoon:
12bits 40mhz pipelined ADC with duty-correction circuit. 441-444 - Gian Nicola Angotzi, Massimo Barbaro
Comparison of redundant architectures for two-step ADCs. 445-450 - Daesun Oh, Keshab K. Parhi
Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes. 451-456 - Zhiqiang Cui, Zhongfeng Wang:
Extended layered decoding of LDPC codes. 457-462
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