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24th FCCM 2016: Washington, DC, USA
- 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016, Washington, DC, USA, May 1-3, 2016. IEEE Computer Society 2016, ISBN 978-1-5090-2356-1
Session 1: Overlays
- Abhishek Kumar Jain
, Xiangwei Li
DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect. 1-8 - Henry Wong, Vaughn Betz, Jonathan Rose:
High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors. 9-16 - Jan Gray:
GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator. 17-20 - Dustin Richmond
Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler. 21-24
Posters 1
- Gopalakrishna Hegde, Siddhartha, Nachiappan Ramasamy, Vamsi Buddha, Nachiket Kapre:
Evaluating Embedded FPGA Accelerators for Deep Learning Applications. 25 - Nachiket Kapre, Siddhartha:
Communication Optimization for the 16-Core Epiphany Floating-Point Processor Array. 26 - Andreas Becher
A LUT-Based Approximate Adder. 27 - Ernst Joachim Houtgast, Vlad Mihai Sima
Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms. 28 - Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei, Peng Wei:
When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration. 29 - Kohei Nagasu, Kentaro Sano, Fumiya Kono, Naohito Nakasato, Alexander Vazhenin, Stanislav G. Sedukhin:
Parallelism for High-Performance Tsunami Simulation with FPGA: Spatial or Temporal? 30 - Tianqi Wang, Xi Jin, Bo Peng, Chuanjun Wang, Linlin Zheng:
RP-Ring: A Heterogeneous Multi-FPGA Accelerating Solution for N-Body Simulations. 31
Session 2: Applications 1 (Artificial Neural Networks and Computational Biology)
- Mau-Chung Frank Chang
The SMEM Seeding Acceleration for DNA Sequence Alignment. 32-39 - Stylianos I. Venieris
fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs. 40-47 - Jiang Su, David B. Thomas
Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout. 48-51 - Jordan A. Bradshaw, Rasha Karakchi, Jason D. Bakos:
Two-Hit Filter Synthesis for Genomic Database Search. 52-55
Session 3: CAD, Synthesis, and Compilers 1
- Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. 56-63 - Zeping Xue, David B. Thomas
SynADT: Dynamic Data Structures in High Level Synthesis. 64-71 - Junyi Liu, John Wickerson
Loop Splitting for Efficient Pipelining in High-Level Synthesis. 72-79 - Que Yanghua, Nachiket Kapre, Harnhua Ng, Kirvy Teo:
Improving Classification Accuracy of a Machine Learning Approach for FPGA Timing Closure. 80-83 - Maciej Kurek, Marc Peter Deisenroth, Wayne Luk, Timothy John Todman
Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs. 84-87 - Dimitris Agiakatsikas
Reconfiguration Control Networks for TMR Systems with Module-Based Recovery. 88-91
Posters 2
- Nina Engelhardt, Hayden Kwok-Hay So
Vertex-Centric Graph Processing on FPGA. 92 - William Diehl, Kris Gaj:
High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two. 93 - Ehsan Ghasemi, Paul Chow:
Accelerating Apache Spark Big Data Analysis with FPGAs. 94
Session 4: Applications 2 (Data-centric Energy Efficiency)
- Wei Song
Parallel Hardware Merge Sorter. 95-102 - Shijie Zhou, Charalampos Chelmis
High-Throughput and Energy-Efficient Graph Processing on FPGA. 103-110
Session 5: Hardware Debug
- Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon:
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). 111-118 - Dana L. How
Sectors: Divide & Conquer and Softwarization in the Design and Validation of the Stratix® 10 FPGA. 119-126 - Liwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow:
AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS. 127-130 - Tao Li, Qiang Liu:
Cost Effective Partial Scan for Hardware Emulation. 131-134
Posters 3
- Bajaj Ronak, Suhaib A. Fahmy:
Initiation Interval Aware Resource Sharing for FPGA DSP Blocks. 135 - Marco Minutoli
A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries. 136 - Gowthami Jayashri Manikandan, Sitao Huang, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen:
Acceleration of the Pair-HMM Algorithm for DNA Variant Calling. 137 - Farheen Fatima Khan, Andy Ye:
An Empirical Analysis of the Fidelity of VPR Area Models. 138 - Amine Ait Si Ali
Heterogeneous Implementation of ECG Encryption and Identification on the Zynq SoC. 139
Session 6: CAD, Synthesis, and Compilers 2
- Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs. 140-147 - Pavel Benácek, Viktor Pus, Hana Kubátová:
P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers. 148-155 - Nachiket Kapre:
Marathon: Statically-Scheduled Conflict-Free Routing on FPGA Overlay NoCs. 156-163 - Chuyu Shen, Zili Lin, Ping Fan, Xianglong Meng, Weikang Qian:
Parallelizing FPGA Technology Mapping through Partitioning. 164-167 - Seyyed Mahdi Najmabadi, Zhe Wang, Yousef Baroud, Sven Simon:
Online Bandwidth Reduction Using Dynamic Partial Reconfiguration. 168-171 - Peipei Zhou
Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication. 172-175
Session 7: Applications 3 (Computational Physics and Geography)
- Dajung Lee, Roger Moussalli, Sameh W. Asaad, Mudhakar Srivatsa:
Spatial Predicates Evaluation in the Geohash Domain Using Reconfigurable Hardware. 176-183 - Tanja Harbaum
A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment. 184-191 - Ahmed Sanaullah, Arash Khoshparvar, Martin C. Herbordt:
FPGA-Accelerated Particle-Grid Mapping. 192-195
Posters 4
- Thaddeus Koehn, Peter M. Athanas:
Finding Space-Time Stream Permutations for Minimum Memory and Latency. 196 - Jiayi Sheng, Qingqing Xiong, Chen Yang, Martin C. Herbordt:
Application-Aware Collective Communication (Extended Abstract). 197 - Konstantinos Krommydas, Ahmed E. Helal, Anshuman Verma, Wu-chun Feng:
Bridging the Performance-Programmability Gap for FPGAs via OpenCL: A Case Study with OpenDwarfs. 198 - Zhiyuan Yang, Caleb Serafy, Ankur Srivastava
ECO Based Placement and Routing Framework for 3D FPGAs with Micro-fluidic Cooling. 199 - Adam Page, Tinoosh Mohsenin:
FPGA-Based Reduction Techniques for Efficient Deep Neural Network Deployment. 200 - Amey M. Kulkarni, Ali Jafari, Colin Shea, Tinoosh Mohsenin:
CS-Based Secured Big Data Processing on FPGA. 201 - Amine Ait Si Ali
High Level Synthesis Based E-Nose System for Gas Applications. 202-203
Session 8: Applications 4 ("Big Data")
- Zsolt István, David Sidler, Gustavo Alonso:
Runtime Parameterizable Regular Expression Operators for Databases. 204-211 - Ren Chen, Viktor K. Prasanna:
Accelerating Equi-Join on a CPU-FPGA Heterogeneous Platform. 212-219
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