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20th FCCM 2012: Toronto, Ontario, Canada
- 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012, 29 April - 1 May 2012, Toronto, Ontario, Canada. IEEE Computer Society 2012, ISBN 978-0-7695-4699-5
Architecture
- Oriol Arcas
, Philipp Kirchhofer, Nehir Sönmez
A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory. 1-8 - Srinidhi Kestur, John D. Davis, Eric S. Chung:
Towards a Universal FPGA Matrix-Vector Multiplication Architecture. 9-16 - Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski:
Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems. 17-24 - Manish Kumar Jaiswal, Ray C. C. Cheung
Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers. 25-28 - Eduardo Gudis, Gooitzen S. van der Wal, Sujit Kuthirummal, Sek M. Chai:
Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA. 29-32 - Gary C. T. Chow, Wayne Luk, Philip Heng Wai Leong
A Mixed Precision Methodology for Mathematical Optimisation. 33-36
Reconfiguration
- Christian Beckhoff, Dirk Koch, Jim Tørresen:
Go Ahead: A Partial Reconfiguration Framework. 37-44 - Christopher Dennl, Daniel Ziener
On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library. 45-52 - Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan:
Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing. 53-60 - Spyros Lyberis, George Kalokerinos, Michalis Lygerakis, Vassilis Papaefstathiou, Dimitrios Tsaliagkos, Manolis Katevenis, Dionisios N. Pnevmatikatos
Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures. 61-64 - Kumud Nepal, Onur Ulusel, R. Iris Bahar
Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. 65-68
Applications 1
- Xiaolin Chen, Andreas Minwegen, Yahia Hassan, David Kammler, Shuai Li, Torsten Kempf, Anupam Chattopadhyay, Gerd Ascheid:
FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP. 69-76 - Hélène Martorell, Nachiket Kapre
FX-SCORE: A Framework for Fixed-Point Compilation of SPICE Device Models Using Gappa++. 77-84 - Mihalis Psarakis, Aggelos Pikrakis
FPGA-based Acceleration for Tracking Audio Effects in Movies. 85-92 - Alexander Brant, Guy G. F. Lemieux:
ZUMA: An Open FPGA Overlay Architecture. 93-96 - Jing Yan, Zhanxiang Zhao, Ning-Yi Xu, Xi Jin, Lin-Tao Zhang, Feng-Hsiung Hsu:
Efficient Query Processing for Web Search Engine with FPGAs. 97-100
Power and Measurement
- Moritz Schmid, Frank Hannig
Power Management Strategies for Serial RapidIO Endpoints in FPGAs. 101-108 - Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. 109-116 - Yamuna Rajasekhar, Rahul R. Sharma, Ron Sass:
An Extensible and Portable Tool Suite for Managing Multi-Node FPGA Systems. 117-120 - Rémi Busseuil, Luciano Ost
Remote Execution in Distributed Memory MPSoC. 121-124
Applications 2
- Isaac Liu, Edward A. Lee
A Heterogeneous Architecture for Evaluating Real-Time One-Dimensional Computational Fluid Dynamics on FPGAs. 125-132 - Simon W. Moore
Bluehive - A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation. 133-140 - Srinidhi Kestur, Mi Sun Park, Jagdish Sabarad, Dharav Dantara, Vijaykrishnan Narayanan, Yang Chen, Deepak Khosla:
Emulating Mammalian Vision on Reconfigurable Hardware. 141-148 - Gabriel L. Nazar, Luigi Carro
Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs. 149-152 - Grigorios Mingas, Christos-Savvas Bouganis
A Custom Precision Based Architecture for Accelerating Parallel Tempering MCMC on FPGAs without Introducing Sampling Error. 153-156 - Shaoyi Cheng, Mingjie Lin, Hao Jun Liu, Simon Scott, John Wawrzynek:
Exploiting Memory-Level Parallelism in Reconfigurable Accelerators. 157-160
Bioinfomatics
- Corey B. Olson, Maria Kim, Cooper Clauson, Boris Kogon, Carl Ebeling, Scott Hauck, Walter L. Ruzzo
Hardware Acceleration of Short Read Mapping. 161-168 - Thomas B. Preußer, Oliver Knodel
Short-Read Mapping by a Systolic Custom FPGA Computation. 169-176 - Atabak Mahram, Martin C. Herbordt:
FMSA: FPGA-Accelerated ClustalW-Based Multiple Sequence Alignment through Pipelined Prefiltering. 177-183 - Wen Tang, Wendi Wang, Bo Duan, Chunming Zhang
Accelerating Millions of Short Reads Mapping on a Heterogeneous Architecture with FPGA Accelerator. 184-187 - Berkin Akin, Peter A. Milder
Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes. 188-191
Compilers and Systems
- João M. P. Cardoso
Specifying Compiler Strategies for FPGA-based Systems. 192-199 - Pascal Cotret, Jérémie Crenne, Guy Gogniat
Bus-based MPSoC Security through Communication Protection: A Latency-efficient Alternative. 200-207 - Lars Bauer, Artjom Grudnitsky, Muhammad Shafique
PATS: A Performance Aware Task Scheduler for Runtime Reconfigurable Processors. 208-215 - Matthew Jacobsen, Yoav Freund, Ryan Kastner
RIFFA: A Reusable Integration Framework for FPGA Accelerators. 216-219 - Louis Woods, Ken Eguro:
Groundhog - A Serial ATA Host Bus Adapter (HBA) for FPGAs. 220-223
GPUs and Data Parallelisms
- Gabriel Falcão
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case. 224-231 - Brian Van Essen, Chris Macaraeg, Maya B. Gokhale, Ryan Prenger:
Accelerating a Random Forest Classifier: Multi-Core, GP-GPU, or FPGA? 232-239
Poster Papers
- George Eichinger, Kaushik R. Chowdhury
Cognitive Radio Universal Software Hardware. 240 - Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams. 241 - Andreas Ehliar:
EBRAM - Extending the BlockRAMs in FPGAs to Support Caches and Hash Tables in an Efficient Manner. 242 - Mary Ellen Tie, Miriam Leeser:
Implementing Murf: Accelerating Large State Space Exploration on FPGAs. 243 - Joseph G. Wingbermuehle, Roger D. Chamberlain, Ron K. Cytron:
ScalaPipe: A Streaming Application Generator. 244 - Aaron Severance, Guy Lemieux:
VENICE: A Compact Vector Processor for FPGA Applications. 245
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