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ETS 2014: Paderborn, Germany
- Giorgio Di Natale:
19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014. IEEE 2014, ISBN 978-1-4799-3415-7 - Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi:
Improving polynomial datapath debugging with HEDs. 1-6 - Richard Swanson, Anna Wong, Suraj Ethirajan, Amitava Majumdar:
Avoiding burnt probe tips: Practical solutions for testing internally regulated power supplies. 1-6 - Marzieh Mohammadi, Somayeh Sadeghi Kohan, Nasser Masoumi, Zainalabedin Navabi:
An off-line MDSI interconnect BIST incorporated in BS 1149.1. 1-2 - Álvaro Gómez-Pau, Luz Balado, Joan Figueras:
M-S specification binning based on digitally coded indirect measurements. 1-6 - Anthi Anastasiou, Yiorgos Tsiatouhas
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Power efficient scan testing by exploiting existing error tolerance circuitry in a design. 1-2 - Asen Asenov:
Factoring variability in the Design/Technology Co Optimisation (DTCO) in advanced CMOS. 1 - Adit D. Singh:
Error detection and recovery in better-than-worst-case timing designs. 1-6 - Shudong Lin, Gordon W. Roberts:
Towards a general purpose mixed-signal instrumentation layer in the die stack of a 3D-SIC. 1-2 - Amr A. R. Sayed-Ahmed, Hossam A. H. Fahmy, Ulrich Kühne:
Verification of the decimal floating-point square root operation. 1-2 - Horst Schirmeier
Smart-hopping: Highly efficient ISA-level fault injection on real hardware. 1-6 - Marcus Wagner, Hans-Joachim Wunderlich:
Incremental computation of delay fault detection probability for variation-aware test generation. 1-6 - Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri
iBoX - Jitter based Power Supply Noise sensor. 1-2 - Sarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao:
Property-checking based LBIST for improved diagnosability. 1-2 - Kuan-Yu Liao, Po-Juei Chen, Ang-Feng Lin, James Chien-Mo Li, Michael S. Hsiao, Laung-Terng Wang:
GPU-based timing-aware test generation for small delay defects. 1-2 - Yaara Neumeier
A new efficiency criterion for security oriented error correcting codes. 1-6 - Alejandro Cook, Hans-Joachim Wunderlich:
Diagnosis of multiple faults with highly compacted test responses. 1-6 - Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Optimization-based multiple target test generation for highly compacted test sets. 1-6 - Luca Sterpone
Analysis and mitigation of single event effects on flash-based FPGAS. 1-6 - Christian Badack, Michael Gössel:
Triple error detection for Imai-Kamiyanagi codes based on subsyndrome computations. 1-2 - Davide Sabena, Luca Sterpone
Reconfigurable high performance architectures: How much are they ready for safety-critical applications? 1-8 - Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi:
Automatic correction of certain design errors using mutation technique. 1-2 - Eberhard Böhl, Matthew Lewis, Klaus Damm:
A collision resistant deterministic random bit generator with fault attack detection possibilities. 1-2 - Ioannis Voyiatzis:
Accumulator-based test-per-clock scheme for low-power on-chip application of test patterns. 1-2 - Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner
Shadow-scan design with low latency overhead and in-situ slack-time monitoring. 1-6 - Friedrich Hapke, Ralf Arnold, Matthias Beck, M. Baby, S. Straehle, J. F. Goncalves, A. Panait, R. Behr, Gwenolé Maugard, A. Prashanthi, Juergen Schloeffel, Wilfried Redemund, Andreas Glowatz, Anja Fast, Janusz Rajski:
Cell-aware experiences in a high-quality automotive test suite. 1-6 - Jia Li, Zhuolei Huang, Weibing Wang:
Built-in self-calibration of CMOS-compatible thermopile sensor with on-chip electrical stimulus. 1-6 - Xijiang Lin, Mark Kassab, Janusz Rajski:
Using dynamic shift to reduce test data volume in high-compression designs. 1-6 - Ilia Polian, Jie Jiang, Adit D. Singh:
Detection conditions for errors in self-adaptive better-than-worst-case designs. 1-6 - Wei-Cheng Lien
Output-bit selection with X-avoidance using multiple counters for test-response compaction. 1-6 - Suvadeep Banerjee
Design of low cost fault tolerant analog circuits using real-time learned error compensation. 1-2 - Ioannis Voyiatzis:
Concurrent online BIST for sequential circuits exploiting input reduction and output space compaction. 1-2 - Athul Prabhu, Vlado Vorisek, Helmut Lang, Thomas Schumann:
Analysis of cell-aware test pattern effectiveness - A case study using a 32-bit automotive microcontroller. 1-2 - Luca Cassano
A novel adaptive fault tolerant flip-flop architecture based on TMR. 1-2 - Mehdi Dehbashi, Görschwin Fey
Sat-based speedpath debugging using waveforms. 1-6 - Matthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker
Variation-aware deterministic ATPG. 1-6 - Fernanda Lima Kastensmidt
Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs. 1-2 - Sk Subidh Ali
Test-mode-only scan attack using the boundary scan chain. 1-6 - Anthony Coyette, Georges G. E. Gielen
Optimization of analog fault coverage by exploiting defect-specific masking. 1-6 - Thomas Lehner, Andreas Kuhr, Michael G. Wahl, Rainer Brück:
Site dependencies in a multisite testing environment. 1-6 - Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng:
On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs. 1-2 - Elena Dubrova, Mats Näslund, Göran Selander:
Secure and efficient LBIST for feedback shift register-based cryptographic systems. 1-6 - Thomas Herrmann, Shobhit Malik, Sriram Madhavan
Quantified contribution of design for manufacturing to yield at 28nm. 1-6 - Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus:
Systematic generation of diagnostic software-based self-test routines for processor components. 1-6 - Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis:
A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis. 1-2 - Marco Indaco, Paolo Prinetto, Elena I. Vatajelu
On the impact of process variability and aging on the reliability of emerging memories (Embedded tutorial). 1-10 - Eberhard Böhl, Matthew Lewis, S. Galkin:
A true random number generator with on-line testability. 1-6 - Eduardo J. Peralías
INL systematic reduced-test technique for Pipeline ADCs. 1-6 - Walden C. Rhines:
Major eras of Design for Test. 1 - Thiago Santini, Paolo Rech
Reducing embedded software radiation-induced failures through cache memories. 1-6 - Arezoo Kamran
Homogeneous many-core processor system test distribution and execution mechanism. 1-2 - Orlando Ferrante, Alberto Ferrari, Marco Marazza:
Model based generation of high coverage test suites for embedded systems. 1-2 - Dan Alexandrescu, Luca Sterpone
Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation. 1-6 - Madalin Neagu
Interleaved scrambling technique: A novel low-power security layer for cache memories. 1-2 - Alireza Rohani, Hans G. Kerkhoff:
Two soft-error mitigation techniques for functional units of DSP processors. 1-6 - Irith Pomeranz:
A distance-based test cube merging procedure for compatible and incompatible test cubes. 1-2 - Dmitri Mironov
Logic simulation and fault collapsing with shared structurally synthesized bdds. 1-2 - Rosa Rodríguez-Montañés, Daniel Arumí
Post-bond test of Through-Silicon Vias with open defects. 1-6 - Liang Chen, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Quantitative evaluation of register vulnerabilities in RTL control paths. 1-2
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