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Kuan-Yu Liao
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2020 – today
- 2023
- [j4]Yu-Cheng Fan
, Kuan-Yu Liao, You-Sheng Xiao, Min-Hua Lu, Wei-Zhe Yan:
3D Point Cloud Semantic Segmentation System Based on Lightweight FPConv. IEEE Access 11: 31767-31777 (2023) - [j3]Tsung-Heng Tsai
A 180 nA Quiescent Current Digital Control Dual-Mode Buck Converter With a Pulse-Skipping Load Detector for Long-Range Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 3040-3048 (2023) - 2022
- [c10]Kuan-Yu Liao, You-Sheng Xiao, Yu-Cheng Fan:
3D Point Cloud Semantic Segmentation System. ICCCM 2022: 68-72 - [c9]Tsung-Wen Sun
A Digital-Control Buck Converter with Dual Pulse-Skipping Modes for Internet of Things. ISCAS 2022: 2516-2519 - [c8]Kuan-Yu Liao, Min-Hua Lu, Yu-Cheng Fan:
3D Point-cloud Segmentation System Based on AI Model. LifeTech 2022: 433-434 - 2021
- [c7]Guo-Han Lin, You-Sheng Xiao, Hao-An Hsieh, Kuan-Yu Liao, Yi-Cheng Liu, Yu-Cheng Fan:
3D Point Cloud Matching Technology Based on Depth Image Based Rendering. ICCE 2021: 1-2
2010 – 2019
- 2015
- [c6]Ang-Feng Lin, Kuan-Yu Liao, Kuan-Ying Chiang, James Chien-Mo Li:
TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects. VLSI-DAT 2015: 1-4 - 2014
- [c5]Kuan-Yu Liao, Po-Juei Chen, Ang-Feng Lin, James Chien-Mo Li, Michael S. Hsiao, Laung-Terng Wang:
GPU-based timing-aware test generation for small delay defects. ETS 2014: 1-2 - 2013
- [j2]Chia-Yuan Chang, Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li, Jiann-Chyi Rau:
Compact Test Pattern Selection for Small Delay Defect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 971-975 (2013) - [c4]Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li:
GPU-based n-detect transition fault ATPG. DAC 2013: 28:1-28:8 - [c3]Shin-Yann Ho, Shuo-Ren Lin, Ko-Lung Yuan, Chien-Yen Kuo, Kuan-Yu Liao, Jie-Hong R. Jiang, Chien-Mo James Li:
Automatic test pattern generation for delay defects using timed characteristic functions. ICCAD 2013: 91-98 - 2011
- [j1]Kuan-Yu Liao, Chia-Yuan Chang, James Chien-Mo Li:
A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1767-1772 (2011) - [c2]Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James Chien-Mo Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li:
Test clock domain optimization for peak power supply noise reduction during scan. ITC 2011: 1-8
2000 – 2009
- 2009
- [c1]Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng:
BIST design optimization for large-scale embedded memory cores. ICCAD 2009: 197-200
Coauthor Index
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