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DFT 2007: Rome, Italy
- Cristiana Bolchini, Yong-Bin Kim, Adelio Salsano, Nur A. Touba:
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy. IEEE Computer Society 2007, ISBN 0-7695-2885-6
Session 1 - Reliable NoCs and SoCs
- Avijit Dutta, Nur A. Touba:
Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code. 3-11 - Young Bok Kim, Yong-Bin Kim:
Fault Tolerant Source Routing for Network-on-Chip. 12-20 - Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi:
Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode. 21-30 - Abderrahim Doumar, Kentaroh Katoh, Hideo Ito:
Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. 31-40
Session 2 - Single Event Effects
- Hossein Asadi
, Mehdi Baradaran Tahoori, Chandra Tirumurti:
Estimating Error Propagation Probabilities with Bounded Variances. 41-49 - Sybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube:
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. 50-58 - Rani S. Ghaida, Payman Zarkesh-Ha:
Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model. 59-67 - Mario García-Valderas
SET Emulation Under a Quantized Delay Model. 68-77
Session 3 - Defect and Fault Tolerance
- Andrea Manuzzato, Paolo Rech
Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs. 79-86 - Cristiana Bolchini
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs. 87-95 - Salvatore Pontarelli
Optimization of Self Checking FIR filters by means of Fault Injection Analysis. 96-104
Session 4 - Fault Injection and Reliability Analysis
- Monica Alderighi
Evaluation of Single Event Upset Mitigation Schemes for SRAM Based FPGAs Using the FLIPPER Fault Injection Platform. 105-113 - Alfredo Benso, Alberto Bosio, Stefano Di Carlo
A Functional Verification Based Fault Injection Environment. 114-122 - Riccardo Mariani, Peter Fuhrmann:
Comparing fail-safe microcontroller architectures in light of IEC 61508. 123-131 - Giovanni Beltrame, Cristiana Bolchini
A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip. 132-141
Interactive Poster Session
- Yoon-Hwa Choi, Myeong-Hyeon Lee:
A Defect-Tolerant Molecular-Based Memory Architecture. 143-151 - Martin Straka, Jiri Tobola, Zdenek Kotásek:
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols. 152-160 - Ravi Bonam, Yong-Bin Kim, Minsu Choi:
Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture. 161-169 - Michele Favalli
Delay Fault Detection Problems in Circuits Featuring a Low Combinational Depth. 170-178 - Mehdi Kamal, Somayyeh Koohi, Shaahin Hessabi
Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs. 179-187 - Mojtaba Valinataj
Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction. 188-196 - Piotr Zajac
Production Yield and Self-Configuration in the Future Massively Defective Nanochips. 197-205 - Anjela Yu. Matrosova, Ekaterina Loukovnikova, Sergei Ostanin, Alexandra Zinchuk, Ekaterina Nikolaeva:
Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs. 206-214 - Waleed K. Al-Assadi, Sindhu Kakarla:
Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Design. 215-222 - Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu:
Timing-Aware Diagnosis for Small Delay Defects. 223-234
Session 5 - Testing and Design for Testability
- Irith Pomeranz, Sudhakar M. Reddy:
A-Diagnosis: A Complement to Z-Diagnosis. 235-242 - Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. 243-251 - Abhijit Jas, Srinivas Patil:
Analysis of Specified Bit Handling Capability of Combinational Expander Networks. 252-260 - Ilya Levin
Reduction of Fault Latency in Sequential Circuits by using Decomposition. 261-271
Session 6 - Soft Errors
- Weidong Kuang, Casto Manuel Ibarra, Peiyi Zhao:
Soft Error Hardening for Asynchronous Circuits. 273-281 - Takashi Ikeda, Kazuteru Namba, Hideo Ito:
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. 282-290 - Jorge Luis Lagos-Benites
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains. 291-300
Session 7 - Defect and Fault Tolerance
- Jorge Semião
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations. 303-311 - Laura Frigerio, Fabio Salice:
RAM-Based Fault Tolerant State Machines for FPGAs. 312-320 - Erik Schüler, Adão Antônio de Souza Jr.
Spare Parts in Analog Circuits: A Filter Example. 321-329
Session 8 - Dependable Solutions for Memories and Storage
- Swapnil Bahl:
A Sharable Built-in Self-Repair for Semiconductor Memories with 2-D Redundancy Schema. 331-339 - Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan:
Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. 340-348 - Haruhiko Kaneko, Eiji Fujiwara:
Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks. 349-358
Session 9 - Reliable Design Techniques
- Mahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J. Sorin:
Lazy Error Detection for Microprocessor Functional Units. 361-369 - Michele Portolan, Régis Leveugle:
Effective Checkpoint and Rollback Using Hardware/OS Collaboration. 370-378 - George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors. 379-387
Session 10 - Emerging Technologies - 1
- Masaru Fukushi, Susumu Horiguchi, Luke Demoracski, Fabrizio Lombardi:
A Scalable Framework for Defect Isolation of DNA Self-assemlbled Networks. 391-399 - Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi:
Error Tolerance of DNA Self-Healing Assemblies by Puncturing. 400-408 - Helia Naeimi, André DeHon:
Fault Secure Encoder and Decoder for Memory Applications. 409-417 - Michelangelo Grosso
Safety Evaluation of NanoFabrics. 418-426 - Mandar V. Joshi, Waleed Al-Assadi:
Nanofabric PLA architecture with Redundancy Enhancement. 427-435
Session 11 - Testing
- Stelios Neophytou
Hierarchical Fault Compatibility Identification for Test Generation with a Small Number of Specified Bits. 439-447 - Michele Favalli
High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations. 448-456 - Irith Pomeranz, Sudhakar M. Reddy:
Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits. 457-455
Session 12 - Emerging Technologies - 2
- Jing Huang, Xiaojun Ma, Cecilia Metra, Fabrizio Lombardi:
Testing Reversible One-Dimensional QCA Arrays for Multiple Faults. 469-477 - Timothy J. Dysart, Peter M. Kogge:
Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder. 478-486 - Marco Ottavi
On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata Circuits. 487-495
Session 13 - Reliable Applications
- Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle:
Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections. 499-507 - Francesco Regazzoni
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. 508-516 - Jozsef Dudas, Michelle L. La Haye, Jenny Leung, Glenn H. Chapman:
A Fault-Tolerant Active Pixel Sensor to Correct In-Field Hot Pixel Defects. 517-525 - Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren:
Quantitative Analysis of In-Field Defects in Image Sensor Arrays. 526-534
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