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38th DCIS 2023: Málaga, Spain
- 38th Conference on Design of Circuits and Integrated Systems, DCIS 2023, Málaga, Spain, November 15-17, 2023. IEEE 2023, ISBN 979-8-3503-0385-8
- Jorge Pérez-Bailón, Santiago Celma, Carlos Sánchez-Azqueta:
CMOS Transistor Array for Cryogenic Temperature Characterization of MOS Components. 1-5 - Marco Hormigo-Jiménez, Javier Hormigo:
High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS. 1-6 - Samuel López Asunción, Pablo Ituero Herrero:
Flexible Deep-pipelined FPGA-based Accelerator for Spiking Neural Networks. 1-6 - Pedro Paz, Mario Garrido:
A 5.2-GS/s 8-Parallel 1024-Point MDC FFT. 1-6 - José-Miguel Galeas-Merchán, José-Borja Castillo-Sánchez
, Martín González-García:
Simplifying RTL design and verification in chip manufacturing: A paradigm for Electronics Teaching using Open-Source tools. 1-6 - Sebastià A. Bota, Salvador Barceló
A Compact Double-Exponential Circuit for Single Event Transient Emulation. 1-6 - Javier Beloso-Legarra, Antonio Lopez-Martin, Carlos Aristoteles De la Cruz, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
GBW Optimization in Two-Stage OTAs Operating in Weak Inversion. 1-4 - Alejandra Sanchez-Flores, Lluc Alvarez, Bartomeu Alorda-Ladaria:
Accelerators in Embedded Systems for Machine Learning: A RISCV View. 1-6 - Apurba Karmakar
HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip. 1-6 - Marine Brun, Gilles Jacquemod, Yoann Charlon, Arnaud Gamet, Philippe Le Fevre:
A Two-Stage Amplifier in a Low Power 32.768 kHz Quartz Crystal Oscillator. 1-6 - Anibal Pacheco-Sanchez, Javier Noé Ramos-Silva
Design of GFET-based active modulators leveraging device performance reproducibility conditions. 1-6 - Rafael Tornero, David Rodriguez, José Maria Martínez, José Flich:
An Open-Source FPGA Platform for Shared-Memory Heterogeneous Many-Core Architecture Exploration. 1-6 - Pedro Barba
ADC Architectural Study for Digitally-Assisted Multi-Gigabit Data Communication Transceivers. 1-5 - Selenia María Medina Hernández, Pedro P. Carballo, Pedro Hernández-Fernández, David S. Miranda Guillén, Sergio González:
SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics. 1-6 - Max Doblas
Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. 1-6 - Simon Skrzypczak, Di Zhou, Wei Wei, Dalal Fadil, Dominique Vignaud, Emiliano Pallecchi, Henri Happy:
Devices and circuits for HF applications based on 2D materials. 1-5 - Daniel Enériz, Nicolás Medrano, Belén Calvo, Diego Antolín:
Low-power EEGNet-based Brain-Computer Interface implemented on an Arduino Nano 33 Sense. 1-5 - Roland Müller, Loreto Mateu, Ralf Brederlow:
Analog/Mixed-Signal Standard Cell Based Approach for Automated Circuit Generation of Neural Network Accelerators. 1-6 - Héctor Posadas, José Luis Vázquez, Eugenio Villar:
Automatic code generation from UML for data memory optimization in microcontrollers. 1-6 - Anderson Aparecido Dionizio, Leonardo Poltronieri Sampaio, Sérgio Augusto Oliveira da Silva:
Integrated Cuk Inverter for Single-Phase Grid-Tied Photovoltaic System. 1-6 - Miguel Cubero, David Moltó, Elena Aparicio-Esteve, Álvaro Hernández, José Manuel Villadangos, Jesús Ureña:
High-Rate Acquisition System for an Infrared LPS. 1-6 - Sara Alonso
Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments. 1-6 - Isabel Ortíz-Ramírez, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona:
Study of foveation mechanisms in Dynamic Vision Sensors. 1-6 - Marko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter
SET and SEU Hardened Clock Gating Cell. 1-6 - Jorge Martín, Laura de Diego, Miguel Tapiador, Álvaro Hernández, Rubén Nieto
Comparative Analysis of Neural Network Implementations for NILM Applications. 1-6 - Ignacio Amat Hernández, Juan A. López:
Any-Radix Efficient Fully-Parallel Implementation of the Fast Fourier Transform on FPGAs. 1-6 - Alberto Ramírez-Bárcenas, Mario García-Valderas, Celia López-Ongil:
Design Space Analysis for a Digital Lock-In Amplifier for Infrared Gas Sensor Signal Acquisition. 1-6 - Miguel Tapiador, Laura de Diego-Otón, Álvaro Hernández, Rubén Nieto
Implementing a CNN in FPGA Programmable Logic for NILM Application. 1-6 - Juan Luis Soler-Fernández, Omar Romera, Ángel Diéguez, Joan Daniel Prades, Oscar Alonso:
An ultra-low power custom IoT node for gas sensing applications. 1-6 - Alba Páez-Montoro, Javier De Mena Pacheco, Marisa López-Vallejo, Celia López-Ongil, Susana Patón:
Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition. 1-6 - Daniel Suárez, Héctor Posadas, Víctor Fernández:
UML-Based Design Flow for Systems with Neural Networks. 1-6 - Víctor M. Navarro, Rubén Nieto
SoC Architecture for Acquisition and Processing of EMG Signals. 1-6 - David Castells-Rufas, Xavier Martorell, Aleix Roca, Alexander Kropotov, Xavier Teruel, Teresa Cervero, John D. Davis:
Ethernet Emulation over PCIe for RISC-V Software Development Vehicles. 1-6 - Gabriel Santana Quintana
Design of SoC FPGA based controller to reduce shadow effects in photovoltaic installations. 1-6 - Albert Cirera, Pere Lluís Miribel-Català, Antonio Rubio, Blas Garrido, Jordi Colomer-Farrarons, Ioannis Vourkas:
Using Current to Drive Two SDC Memristors Connected in Series and in Anti-Series. 1-5 - Lorién López-Villellas
RISC-V for Genome Data Analysis: Opportunities and Challenges. 1-6 - David Moltó, Miguel Cubero, Elena Aparicio-Esteve, Álvaro Hernández, Jose M. Villadangos, Jesús Ureña:
Definition of a SoC Architecture for a High-Rate Correlator Bank. 1-6 - Hasan Moussa, Jessica Gonsalves, Estelle Lauga-Larroze, Sana Ibrahim, Florence Podevin, Sylvain Bourdel, Laurent Fesquet:
Making Digital N-Path Mixers. 1-5 - Andrés Fernando Serrano Reyes, María Teresa Sanz-Pascual, Belén Calvo López, Nicolás Medrano:
Three-Stage Low Dropout Regulator with Enhanced Transient Response and Regulation Performance. 1-5 - Eros Camacho-Ruiz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez
A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem. 1-6 - Christiam F. Frasser, Alejandro Morán
Approximate arithmetic aware training for stochastic computing neural networks. 1-6 - Virginia Zúñiga-González, Erica Tena-Sánchez, Antonio J. Acosta:
A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks. 1-6 - Víctor Manuel Bautista, Mario Garrido:
An Automatic Generator of Non-Power-of-Two SDF FFT Architectures for 5G and Beyond. 1-6 - Camilo A. Ruiz-Beltrán, Adrián Romero-Garcés, M. González, J. A. Rodríguez, Antonio Bandera, Antonio Sánchez-Pedraza:
Real-time iris image quality evaluation implemented in Ultrascale MPSoC. 1-6 - Fabio Galán-Prado, Joan Font-Rosselló, Miquel Roca, Josep L. Rosselló:
Stochastic Computing-based on-chip Training Circuitry for Reservoir Computing Systems. 1-6 - Nicolás Medrano, Diego Antolín, Daniel Enériz, Belén Calvo:
High Resolution Current Measurement Using TMR Sensors. 1-5 - Armando Astarloa, Pedro Fernández, Jesús Lázaro, Mikel Idirin, Sergio Salas:
Time-Sensitive Networking to meet Hard-real Time Boundaries on Edge Intelligence Applications. 1-6
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