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Gabriel Torrens
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2020 – today
- 2024
- [i1]Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, Sebastià A. Bota, Jaume Segura:
SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results. CoRR abs/2402.10917 (2024) - 2023
- [c15]Sebastià A. Bota, Salvador Barceló
, Gabriel Torrens, Rafel Perelló, Jaume Verd
A Compact Double-Exponential Circuit for Single Event Transient Emulation. DCIS 2023: 1-6 - 2022
- [c14]Abdel Alheyasat, Gabriel Torrens
SRAM-cells Reproducibility Metrics for Physical Unclonable Function Applications. DCIS 2022: 1-6 - 2020
- [c13]Abdel Alheyasat, Gabriel Torrens
Selection of SRAM Cells to improve Reliable PUF implementation using Cell Mismatch Metric. DCIS 2020: 1-6 - [c12]Abdel Alheyasat, Gabriel Torrens, Sebastià A. Bota, Bartomeu Alorda:
Bit-Cell Selection Analysis for Embedded SRAM-Based PUF. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [j6]Gabriel Torrens
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors. IEEE Trans. Emerg. Top. Comput. 7(3): 447-455 (2019) - [c11]Abdel Alheyasat, Gabriel Torrens
Weak and Strong SRAM cells analysis in embedded memories for PUF applications. DCIS 2019: 1-6 - 2017
- [j5]Daniel Malagón, Sebastià A. Bota, Gabriel Torrens
Soft error rate comparison of 6T and 8T SRAM ICs using mono-energetic proton and neutron irradiation sources. Microelectron. Reliab. 78: 38-45 (2017) - [c10]Bartomeu Alorda
Evaluation of SRAM cell write margin metrics for lifetime monitoring of BTI-induced Vth drift. DTIS 2017: 1-6 - [c9]Sebastià A. Bota, Jaume Verd
Cantilever NEMS relay-based SRAM devices for enhanced reliability. DTIS 2017: 1-6 - [c8]Bartomeu Alorda
6T CMOS SRAMs reliability monitoring through stability measurements. IOLTS 2017: 93-95 - [c7]Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría
Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells. SMACD 2017: 1-4 - 2016
- [j4]Bartomeu Alorda
An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies. Microelectron. Reliab. 65: 280-288 (2016) - [c6]Bartomeu Alorda
On-line write margin estimator to monitor performance degradation in SRAM cores. IOLTS 2016: 90-95 - 2014
- [j3]Bartomeu Alorda
Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells. Microelectron. Reliab. 54(11): 2613-2620 (2014) - 2013
- [c5]Sebastià A. Bota
Accurate alpha soft error rate evaluation in SRAM memories. IOLTS 2013: 205-209 - 2011
- [j2]Bartomeu Alorda
8T vs. 6T SRAM cell radiation robustness: A comparative analysis. Microelectron. Reliab. 51(2): 350-359 (2011) - [c4]Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura:
Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation. DATE 2011: 986-991 - 2010
- [j1]Gabriel Torrens
Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination. IEEE Trans. Circuits Syst. II Express Briefs 57-II(4): 280-284 (2010) - [c3]Bartomeu Alorda, Gabriel Torrens
Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs. DATE 2010: 429-434 - [c2]Sebastià A. Bota
Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories. IOLTS 2010: 141-146
2000 – 2009
- 2009
- [c1]Sebastià A. Bota
Critical charge characterization in 6-T SRAMs during read mode. IOLTS 2009: 120-125
Coauthor Index
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