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DASIP 2017: Dresden, Germany
- 2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017, Dresden, Germany, September 27-29, 2017. IEEE 2017, ISBN 978-1-5386-3534-6
- Steffen Vaas, Peter Ulbrich
, Marc Reichenbach
The best of both: High-performance anc deterministic real-time executive by application-specific multi-core SoCs. 1-6 - Marc Reichenbach
LibHSA: One step towards mastering the era of heterogeneous hardware accelerators using FPGAs. 1-6 - Seyyed Mahdi Najmabadi, Harsimran Singh Tungal, Trung-Hieu Tran, Sven Simon:
Hardware-based architecture for asymmetric numeral systems entropy decoder. 1-6 - Seher Colak, Emmanuel Dumas, Virginie Fresse, Olivier Alata:
Proposition and evaluation of a real-time generic architecture for a laser stripe detection system on FPGA. 1-6 - Raquel Lazcano, Daniel Madroñal
Parallel implementation of an iterative PCA algorithm for hyperspectral images on a manycore platform. 1-6 - Daniel Madroñal
Energy consumption characterization of a Massively Parallel Processor Array (MPPA) platform running a hyperspectral SVM classifier. 1-6 - Aya Ibrahim, William Andrew Simon, Damien Doy, Eliéva Pignat, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran
Single-FPGA complete 3D and 2D medical ultrasound imager. 1-6 - Omar W. Ibraheem, Arif Irwansyah, Jens Hagemeyer, Mario Porrmann
Reconfigurable vision processing system for player tracking in indoor sports. 1-6 - Tien Thanh Nguyen, Anthony Mouraud, Mathieu Thevenin
Model-driven reliability evaluation for MPSoC design. 1-6 - Ben H. H. Juurlink, Jan Lucas, Nadjib Mammeri, Georgios Keramidas, Katerina Pontzolkova, Ignacio Aransay, Chrysa Kokkala, Martyn Bliss, Andrew Richards:
Enabling GPU software developers to optimize their applications - The LPGPU2 approach. 1-6 - Imran Wali, Emmanuel Casseau, Arnaud Tisserand:
An efficient framework for design and assessment of arithmetic operators with Reduced-Precision Redundancy. 1-6 - Sudeep Kanur
Detecting data-parallel synchronous dataflow graphs. 1-6 - Maxime Martelli, Nicolas Gac, Alain Mérigot, Cyrille Enderli:
3D tomography back-projection parallelization on FPGAs using opencl. 1-6 - Mohamad-Al-Fadl Rihani, Jean-Christophe Prévotet
Demo: WIFI-WiMax vertical handover on an ARM-FPGA platform with partial reconfiguration. 1-2 - Javier Arcenegui
Demonstrator of a fingerprint recognition algorithm into a low-power microcontroller. 1-2 - Tomasz Kryjak
Hardware-software abandoned object detection vision system in heterogeneous zynq device. 1-2 - Marcin Kowalczyk, Tomasz Kryjak
Object tracking with the use of a moving camera implemented in heterogeneous zynq SoC - A demo. 1-2 - Florian Fricke, André Werner, Michael Hübner:
Tool flow for automatic generation of architectures and test-cases to enable the evaluation of CGRAs in the context of HPC applications. 1-2 - Florian Kastner, Benedikt Janßen, Sebastian Schwanewilms, Michael Hübner:
A rapid control prototyping platform methodology for decentralized automation. 1-2 - David Gibson, Neill W. Campbell
Adaptive space-time structural coherence for selective imaging. 1-6 - Sebastian Vogel, Andre Guntoro
Efficient hardware acceleration for approximate inference of bitwise deep neural networks. 1-6 - Deepayan Bhowmik, Paulo Garcia
Power efficient dataflow design for a heterogeneous smart camera architecture. 1-6 - Tobias Lieske, Wilfried Uhring
Embedded fluorescence lifetime determination for high throughput real-time droplet sorting with microfluidics. 1-6 - Lester Kalms, Jens Rettkowski, Marc Hamme, Diana Göhringer:
Robust lane recognition for autonomous driving. 1-6 - Bibek Kabi
An overflow free fixed-point eigenvalue decomposition algorithm: Case study of dimensionality reduction in hyperspectral images. 1-9
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