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Mathieu Thevenin
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2020 – today
- 2022
- [c9]Sankari Balasubramaniyan, Mathieu Thevenin, Frédéric Amiel, Maria Trocan:
Graphene Detection System. MEDES 2022: 64-69 - 2021
- [c8]Sankari Balasubramaniyan, François Parmentier, Preden Roulleau, Mathieu Thevenin, Alexis Brenes, Maria Trocan:
Detection of Monolayer Graphene. ICCCI 2021: 784-791 - 2020
- [j4]Robert M. French, Vesna Simic
, Mathieu Thevenin
Peak correlation classifier (PCC) applied to FTIR spectra: a novel means of identifying toxic substances in mixtures. IET Signal Process. 14(10): 737-744 (2020)
2010 – 2019
- 2019
- [j3]Mathieu Thevenin
A templated programmable architecture for highly constrained embedded HD video processing. J. Real Time Image Process. 16(1): 143-160 (2019) - 2018
- [c7]Tien Thanh Nguyen, Mathieu Thevenin, Anthony Mouraud, Gwenolé Corre, Olivier Pasquier, Sébastien Pillement:
High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques. IPDPS Workshops 2018: 202-205 - 2017
- [c6]Tien Thanh Nguyen, Anthony Mouraud, Mathieu Thevenin
Model-driven reliability evaluation for MPSoC design. DASIP 2017: 1-6 - 2016
- [c5]Satyajit Das
A Scalable Design Approach to Efficiently Map Applications on CGRAs. ISVLSI 2016: 655-660 - 2014
- [c4]Thomas Peyret
Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations. ASAP 2014: 169-172 - [c3]Thomas Peyret
An automated design approach to map applications on CGRAs. ACM Great Lakes Symposium on VLSI 2014: 229-230 - 2012
- [c2]Frédérick Carrel, Mehdi Gmar, Hermine Lemaire, Vincent Schoepff, Mathieu Thevenin:
GAMPIX: A new generation of gamma camera. DASIP 2012: 1-2 - 2011
- [j2]Mathieu Thevenin
The eISP low-power and tiny silicon footprint programmable video architecture. J. Real Time Image Process. 6(1): 33-46 (2011) - [c1]Matthieu Texier, Erwan Piriou, Mathieu Thevenin
Designing processors using MAsS, a modular and lightweight instruction-level exploration tool. DASIP 2011: 150-155 - 2010
- [j1]Mathieu Thevenin, Michel Paindavoine, Laurent Letellier:
Processeur vidéo programmable pour la téléphonie mobile eISP, une architecture de calcul très basse consommation à faible empreinte silicium pour le traitement vidéo HD. Tech. Sci. Informatiques 29(2): 225-251 (2010)
2000 – 2009
- 2009
- [b1]Mathieu Thevenin:
Conception et validation d'un processeur programmable de traitement du signal à faible consommation et à faible empreinte silicium : application à la vidéo HD sur téléphone mobile. (Design and Validation). University of Burgundy, Dijon, France, 2009
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