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26th ASP-DAC 2021: Tokyo, Japan
- ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 18-21, 2021. ACM 2021, ISBN 978-1-4503-7999-1
1A: University Design Contest I
- Yuncheng Zhang
, Bangan Liu, Xiaofan Gu, Chun Wang, Atsushi Shirane, Kenichi Okada:
A DSM-based Polar Transmitter with 23.8% System Efficiency. 1-2 - Ibrahim Abdo
A 0.41W 34Gb/s 300GHz CMOS Wireless Transceiver. 3-4 - Ryo Onishi, Koki Miyamoto, Korkut Kaan Tokgoz
Capacitive Sensor Circuit with Relative Slope-Boost Method Based on a Relaxation Oscillator. 5-6 - Yi Zhang
28GHz Phase Shifter with Temperature Compensation for 5G NR Phased-array Transceiver. 7-8 - Peter Toth, Hiroki Ishikuro:
An up to 35 dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems. 9-10 - Yi Tan, Yohsuke Shiiki, Hiroki Ishikuro:
Gate Voltage Optimization in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting. 11-12 - Bo Jiao, Jinshan Zhang, Yuanyuan Xie, Shunli Wang, Haozhe Zhu, Xiaoyang Kang, Zhiyan Dong, Lihua Zhang
A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA. 13-14 - Shinya Tanimura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine:
Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers. 15-16
1B: Accelerating Design and Simulation
- Hai-Dang Vu, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Kim Grüttner:
A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoC. 17-22 - Breytner Joseph Fernández-Mesa, Liliana Andrade, Frédéric Pétrot:
Simulation of Ideally Switched Circuits in SystemC. 23-28 - Soowang Park, Jae-Won Nam, Sandeep K. Gupta:
HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks. 29-34
1C: Process-in-Memory for Efficient and Robust AI
- Chirag Sudarshan, Taha Soliman, Cecilia De la Parra, Christian Weis, Leonardo Ecco, Matthias Jung, Norbert Wehn, Andre Guntoro
A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs. 35-42 - Chenguang Zhang
A Quantized Training Framework for Robust and Accurate ReRAM-based Neural Network Accelerators. 43-48 - Dayane Reis
Attention-in-Memory for Few-Shot Learning with Configurable Ferroelectric FET Arrays. 49-54
1D: Validation and Verification
- Vladimir Herdt, Sören Tempel
Mutation-based Compliance Testing for RISC-V. 55-60 - Chia-Chun Lin, Hsin-Ping Yen, Sheng-Hsiu Wei, Pei-Pei Chen, Yung-Chih Chen, Chun-Yao Wang:
A General Equivalence Checking Framework for Multivalued Logic. 61-66 - Mehran Goli
ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs. 67-72
1E: Design Automation Methods for Various Microfluidic Platforms
- Nai-Ren Shih, Tsung-Yi Ho
A Multi-Commodity Network Flow Based Routing Algorithm for Paper-Based Digital Microfluidic Biochips. 73-78 - Yun-Chen Lo, Bing Li, Sooyong Park, Kwanwoo Shin
Interference-Free Design Methodology for Paper-Based Digital Microfluidic Biochips. 79-84 - Gerold Fink, Philipp Ebner
Accurate and Efficient Simulation of Microfluidic Networks. 85-90
2A: University Design Contest II
- Yasuaki Isshiki, Dai Suzuki, Ryo Ishida, Kousuke Miyaji:
A 65nm CMOS Process Li-ion Battery Charging Cascode SIDO Boost Converter with 89% Maximum Efficiency for RF Wireless Power Transfer Receiver. 91-92 - Joshua Alvin, Jian Pang, Atsushi Shirane, Kenichi Okada:
A High Accuracy Phase and Amplitude Detection Circuit for Calibration of 28GHz Phased Array Beamformer System. 93-94 - Wei Deng, Zheng Song, Ruichang Ma, Haikun Jia, Baoyong Chi:
A Highly Integrated Energy-efficient CMOS Millimeter-wave Transceiver with Direct-modulation Digital Transmitter, Quadrature Phased-coupled Frequency Synthesizer and Substrate-Integrated Waveguide E-shaped Patch Antenna. 95-96 - Kota Shiba, Tatsuo Omori, Mototsugu Hamada, Tadahiro Kuroda:
A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS. 97-98 - Tatsuo Omori, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface. 99-100 - Korkut Kaan Tokgoz
Current-Starved Chaotic Oscillator Over Multiple Frequency Decades on Low-Cost CMOS: Towards Distributed and Scalable Environmental Sensing with a Myriad of Nodes. 101-102 - Hideto Kayashima, Hideharu Amano:
TCI Tester: Tester for Through Chip Interface. 103-104 - Peter Toth, Hiroki Ishikuro:
An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept. 105-106
2B: Emerging Non-Volatile Processing-In-Memory for Next Generation Computing
- Shuhang Zhang, Hai Helen Li, Ulf Schlichtmann:
Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars. 107-113 - Xiaoming Chen, Yuping Wu, Yinhe Han:
FePIM: Contention-Free In-Memory Computing Based on Ferroelectric Field-Effect Transistors. 114-119 - Zhaojun Lu, Md Tanvir Arafin
RIME: A Scalable and Energy-Efficient Processing-In-Memory Architecture for Floating-Point Operations. 120-125 - Yuxuan Huang
A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC. 126-131
2C: Emerging Trends for Cross-Layer Co-Design: From Device, Circuit, to Architecture, Application
- Hussam Amrouch
Cross-layer Design for Computing-in-Memory: From Devices, Circuits, to Architectures and Applications. 132-139
2D: Machine Learning Techniques for EDA in Analog/Mixed-Signal ICs
- Jun-Yang Lei, Abhijit Chatterjee:
Automatic Surrogate Model Generation and Debugging of Analog/Mixed-Signal Designs Via Collaborative Stimulus Generation and Machine Learning. 140-145 - Jiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization. 146-151 - Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang
Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks. 152-157 - Tonmoy Dhar, Jitesh Poojary
Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. 158-163
2E: Innovating Ideas in VLSI Routing Optimization
- Wei Li, Yuxiao Qu, Gengjie Chen, Yuzhe Ma, Bei Yu:
TreeNet: Deep Point Cloud Embedding for Routing Tree Construction. 164-169 - Ting-Chou Lin, Devon J. Merrill, Yen-Yi Wu, Chester Holtz, Chung-Kuan Cheng:
A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs. 170-175 - Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young:
Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment. 176-182 - Suwan Kim, Kyeongrok Jo, Taewhan Kim:
Boosting Pin Accessibility Through Cell Layout Topology Diversification. 183-188
3A: ML-Driven Approximate Computing
- Georgios Zervakis, Hassaan Saadat, Hussam Amrouch, Andreas Gerstlauer, Sri Parameswaran, Jörg Henkel:
Approximate Computing for ML: State-of-the-art, Challenges and Visions. 189-196
3B: Architecture-Level Exploration
- Jan Moritz Joseph
Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures. 197-203 - Cheng Li, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei:
Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs. 204-209 - Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang:
A Dynamic Link-latency Aware Cache Replacement Policy (DLRP). 210-215 - Shuxin Zhou, Huandong Wang, Dong Tong:
Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse Scheme. 216-221
3C: Core Circuits for AI Accelerators
- Sahand Salamat, Sumiran Shubhi, Behnam Khaleghi, Tajana Rosing:
Residue-Net: Multiplication-free Neural Network by In-situ No-loss Migration to Residue Number Systems. 222-228 - Song Zhang, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei:
A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating. 229-234 - Susmita Dey Manasi, Sachin S. Sapatnekar:
DeepOpt: Optimized Scheduling of CNN Workloads for ASIC-based Systolic Deep Learning Accelerators. 235-241 - Jun-Shen Wu, Chi-En Wang, Ren-Shuo Liu:
Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators. 242-247
3D: Stochastic and Approximate Computing
- Taylor Kemp, Yao Yao, Younghyun Kim:
MIPAC: Dynamic Input-Aware Accuracy Control for Dynamic Auto-Tuning of Iterative Approximate Computing. 248-253 - Di Wu, Ruokai Yin
Normalized Stability: A Cross-Level Design Metric for Early Termination in Stochastic Computing. 254-259 - Hsuan Hsiao, Joshua San Miguel
Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing. 260-265 - Kit Seng Tam, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
An Efficient Approximate Node Merging with an Error Rate Guarantee. 266-271
3E: Timing Analysis and Timing-Aware Design
- Hao Yan, Xiao Shi, Chengzhen Xuan, Peng Cao, Longxing Shi:
An Adaptive Delay Model for Timing Yield Estimation under Wide-Voltage Range. 272-277 - Kuan-Ming Lai, Tsung-Wei Huang, Pei-Yu Lee, Tsung-Yi Ho
ATM: A High Accuracy Extracted Timing Model for Hierarchical Timing Analysis. 278-283 - TaiYu Cheng, Yukata Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto
Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization. 284-290 - Peng Cao, Wei Bao, Kai Wang, Tai Yang:
A Timing Prediction Framework for Wide Voltage Design with Data Augmentation Strategy. 291-296
4A: Technological Advancements inside the AI chips, and using the AI Chips
- Baibhab Chatterjee
Energy-Efficient Deep Neural Networks with Mixed-Signal Neurons and Dense-Local and Sparse-Global Connectivity. 297-304 - Brian Crafton, Samuel Spetalnick, Arijit Raychowdhury:
Merged Logic and Memory Fabrics for AI Workloads. 305-310 - Ravikumar V. Chakaravarthy, Hyun Kwon, Hua Jiang:
Vision Control Unit in Fully Self Driving Vehicles using Xilinx MPSoC and Opensource Stack. 311-317
4B: System-Level Modeling, Simulation, and Exploration
- Shashank Hegde, Subhash Sethumurugan, Hari Cherupalli, Henry Duwe
Constrained Conservative State Symbolic Co-analysis for Ultra-low-power Embedded Systems. 318-324 - Marie Badaroux, Frédéric Pétrot:
Arbitrary and Variable Precision Floating-Point Arithmetic Support in Dynamic Binary Translation. 325-330 - Lukas Jünger, Carmine Bianco, Kristof Niederholtmeyer, Dietmar Petras, Rainer Leupers:
Optimizing Temporal Decoupling using Event Relevance. 331-337 - Thanh Cong, François Charot:
Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization. 338-343
4C: Neural Network Optimizations for Compact AI Inference
- Souvik Kundu, Mahdi Nazemi, Peter A. Beerel, Massoud Pedram:
DNR: A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs. 344-350 - Dingcheng Yang, Wenjian Yu, Haoyuan Mu, Gary Yao:
Dynamic Programming Assisted Quantization Approaches for Compressing Normal and Robust DNN Models. 351-357 - Junhao Pan, Deming Chen:
Accelerate Non-unit Stride Convolutions with Winograd Algorithms. 358-364 - Cecilia De la Parra, Andre Guntoro
Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling. 365-371
4D: Brain-Inspired Computing
- Sitao Huang, Aayush Ankit, Plínio Silveira, Rodrigo Antunes, Sai Rahul Chalamalasetti, Izzat El Hajj, Dong Eun Kim
Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators. 372-377 - Alberto Parravicini, Francesco Sgherzi
A reduced-precision streaming SpMV architecture for Personalized PageRank on FPGA. 378-383 - Yunhui Guo, Mohsen Imani, Jaeyoung Kang
HyperRec: Efficient Recommender Systems with Hyperdimensional Computing. 384-389 - Yu Ma, Pingqiang Zhou:
Efficient Techniques for Training the Memristor-based Spiking Neural Networks Targeting Better Speed, Energy and Lifetime. 390-395
4E: Cross-Layer Hardware Security
- Huifeng Zhu, Xiaolong Guo, Yier Jin
PCBench: Benchmarking of Board-Level Hardware Attacks and Trojans. 396-401 - Saru Vig, Siew-Kei Lam, Rohan Juneja
Cache-Aware Dynamic Skewed Tree for Fast Memory Authentication. 402-407 - Zhixin Pan, Prabhat Mishra
Automated Test Generation for Hardware Trojan Detection using Reinforcement Learning. 408-413 - Md Toufiq Hasan Anik, Bijan Fadaeinia, Amir Moradi
On the Impact of Aging on Power Analysis Attacks Targeting Power-Equalized Cryptographic Circuits. 414-420
5B: Embedded Operating Systems and Information Retrieval
- Elham Shamsa, Anil Kanduri, Amir M. Rahmani
Energy-Performance Co-Management of Mixed-Sensitivity Workloads on Heterogeneous Multi-core Systems. 421-427 - Lamija Hasanagic, Tin Vidovic, Saad Mubeen, Mohammad Ashjaei, Matthias Becker:
Optimizing Inter-Core Data-Propagation Delays in Industrial Embedded Systems under Partitioned Scheduling. 428-434 - Siqi Shang, Qihong Wu, Tianyu Wang
LiteIndex: Memory-Efficient Schema-Agnostic Indexing for JSON documents in SQLite. 435-440
5C: Security Issues in AI and Their Impacts on Hardware Security
- Chaoqun Shen, Congcong Chen, Jiliang Zhang:
Micro-architectural Cache Side-Channel Attacks and Countermeasures. 441-448 - Qian Xu, Md Tanvir Arafin
Security of Neural Networks from Hardware Perspective: A Survey and Beyond. 449-454 - Ashkan Vakil, Farzad Niknia, Ali Mirzaeian, Avesta Sasan, Naghmeh Karimi:
Learning Assisted Side Channel Delay Test for Detection of Recycled ICs. 455-462 - Norman Chang, Deqi Zhu, Lang Lin, Dinesh Selvakumaran, Jimin Wen, Stephen H. Pan, Wenbo Xia, Hua Chen, Calvin Chow, Gary Chen:
ML-augmented Methodology for Fast Thermal Side-channel Emission Analysis. 463-468
5D: Advances in Logic and High-level Synthesis
- Li-Cheng Zheng, Hao-Ju Chang, Yung-Chih Chen, Jing-Yang Jou:
1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method. 469-474 - Meng-Che Wu, Ai Quoc Dao, Mark Po-Hung Lin
A Novel Technology Mapper for Complex Universal Gates. 475-480 - Omar Ragheb, Jason Helge Anderson:
High-Level Synthesis of Transactional Memory. 481-486
5E: Hardware-Oriented Threats and Solutions in Neural Networks
- Hao Lv, Bing Li, Ying Wang, Cheng Liu, Lei Zhang:
VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial Attack. 487-492 - Navid Khoshavi, Saman Sargolzaei, Yu Bi, Arman Roohi:
Entropy-Based Modeling for Estimating Adversarial Bit-flip Attack Impact on Binarized Neural Network. 493-498 - Yuhang Wang, Song Jin, Tao Li:
A Low Cost Weight Obfuscation Scheme for Security Enhancement of ReRAM Based Neural Network Accelerators. 499-504
6B: Advanced Optimizations for Embedded Systems
- Qin Li, Peiyan Dong, Zijie Yu, Changlu Liu, Fei Qiao, Yanzhi Wang, Huazhong Yang:
Puncturing the memory wall: Joint optimization of network compression with approximate memory for ASR application. 505-511 - Satyabrata Sarangi
Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays. 512-517 - Mingfei Yu, Ruitao Gao, Masahiro Fujita:
A Decomposition-Based Synthesis Algorithm for Sparse Matrix-Vector Multiplication in Parallel Communication Structure. 518-523
6C: Design and Learning of Logic Circuits and Systems
- Sina Boroumand, Christos-Savvas Bouganis, George A. Constantinides:
Learning Boolean Circuits from Examples for Approximate Logic Synthesis. 524-529 - Walter Lau Neto, Matheus Trevisan Moreira, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon:
Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. 530-535 - Bernardo Neuhaus Lignati, Michael Guilherme Jordan, Guilherme Korol, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
Exploiting HLS-Generated Multi-Version Kernels to Improve CPU-FPGA Cloud Systems. 536-541
6D: Hardware Locking and Obfuscation
- Jianqi Chen, Benjamin Carrión Schäfer:
Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures. 542-547 - Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu
ObfusX: Routing Obfuscation with Explanatory Analysis of a Machine Learning Attack. 548-554 - Julian Leonhard, Mohamed Elshamy, Marie-Minerve Louërat, Haralampos-G. D. Stratigopoulos:
Breaking Analog Biasing Locking Techniques via Re-Synthesis. 555-560
6E: Efficient Solutions for Emerging Technologies
- Kazim Ergun, Raid Ayoub, Pietro Mercati
Energy and QoS-Aware Dynamic Reliability Management of IoT Edge Computing Systems. 561-567 - Zhidan Zheng
Light: A Scalable and Efficient Wavelength-Routed Optical Networks-On-Chip Topology. 568-573 - Marcel Walter
One-pass Synthesis for Field-coupled Nanocomputing Technologies. 574-580
7A: Platform-Specific Neural Network Acceleration
- Hongjia Li, Geng Yuan, Wei Niu
Real-Time Mobile Acceleration of DNNs: From Computer Vision to Medical Applications. 581-586 - Li Yang, Deliang Fan:
Dynamic Neural Network to Enable Run-Time Trade-off between Accuracy and Latency. 587-592 - Weiwen Jiang, Jinjun Xiong
When Machine Learning Meets Quantum Computers: A Case Study. 593-598 - Meng Li, Yilei Li, Vikas Chandra:
Improving Efficiency in Neural Network Accelerator using Operands Hamming Distance Optimization. 599-604 - Zhepeng Wang, Yawen Wu, Zhenge Jia
Lightweight Run-Time Working Memory Compression for Deployment of Deep Neural Networks on Resource-Constrained MCUs. 607-614
7B: Toward Energy-Efficient Embedded Systems
- Priyanka Singla, Chandran Goodchild, Smruti R. Sarangi:
EHDSktch: A Generic Low Power Architecture for Sketching in Energy Harvesting Devices. 615-620 - Mohanad Odema, Nafiul Rashid, Mohammad Abdullah Al Faruque:
Energy-Aware Design Methodology for Myocardial Infarction Detection on Low-Power Wearable Devices. 621-626 - Tian Wang, Kun Cao, Junlong Zhou, Gongxuan Zhang, Xiji Wang:
Power-Efficient Layer Mapping for CNNs on Integrated CPU and GPU Platforms: A Case Study. 627-632 - Yi-Shen Chen, Chun-Feng Wu
A Write-friendly Arithmetic Coding Scheme for Achieving Energy-Efficient Non-Volatile Memory Systems. 633-638
7C: Software and System Support for Nonvolatile Memory
- Minxuan Zhou, Mohsen Imani, Yeseong Kim, Saransh Gupta, Tajana Rosing:
DP-Sim: A Full-stack Simulation Infrastructure for Digital Processing In-Memory Architectures. 639-644 - Bo Zhou, Chuanming Ding, Yina Lv, Chun Jason Xue, Qingfeng Zhuge, Edwin H.-M. Sha, Liang Shi:
SAC: A Stream Aware Write Cache Scheme for Multi-Streamed Solid State Drives. 645-650 - Paulo C. Santos, Bruno E. Forlin, Luigi Carro:
Providing Plug N' Play for Processing-in-Memory Accelerators. 651-656 - Shihao Song, Anup Das
Aging-Aware Request Scheduling for Non-Volatile Main Memory. 657-664
7D: Learning-Driven VLSI Layout Automation Techniques
- Benzheng Li
Placement for Wafer-Scale Deep Learning Accelerator. 665-670 - Zhiyao Xie, Rongjian Liang
Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. 671-677 - Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Chin-Hsiung Hsu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen:
Machine Learning-based Structural Pre-route Insertability Prediction and Improvement with Guided Backpropagation. 678-683 - Haoxing Ren, Matthew Fojtik:
Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes. 684-689
7E: DNN-Based Physical Analysis and DNN Accelerator Design
- Vidya A. Chhabria
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. 690-696 - Uday Mallappa, Chung-Kuan Cheng:
GRA-LPO: Graph Convolution Based Leakage Power Optimization. 697-702 - Alexander Montgomerie-Corcoran
DEF: Differential Encoding of Featuremaps for Low Power Convolutional Neural Network Accelerators. 703-708 - Prachi Shukla, Sean S. Nemtzow, Vasilis F. Pavlidis, Emre Salman
Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators. 709-714
8B: Embedded Neural Networks and File Systems
- Tony Givargis:
Gravity: An Artificial Neural Network Compiler for Embedded Applications. 715-721 - Fanruo Meng, Fateme S. Hosseini, Chengmo Yang:
A Self-Test Framework for Detecting Fault-induced Accuracy Drop in Neural Network Accelerators. 722-727 - Ping-Xiang Chen
Facilitating the Efficiency of Secure File Data and Metadata Deletion on SMR-based Ext4 File System. 728-733
8C: Design Automation for Future Autonomy
- Shuang Liang, Changcheng Tang, Xuefei Ning, Shulin Zeng, Jincheng Yu, Yu Wang, Kaiyuan Guo, Diange Yang, Tianyi Lu, Huazhong Yang:
Efficient Computing Platform Design for Autonomous Driving Systems. 734-741 - Bo Yu, Jie Tang, Shaoshan Liu:
On Designing Computing Systems for Autonomous Vehicles: a PerceptIn Case Study. 742-747 - Chia-Ching Fu, Ben-Hau Chia, Chung-Wei Lin:
Runtime Software Selection for Adaptive Automotive Systems. 748-752 - Qi Zhu, Chao Huang, Ruochen Jiao, Shuyue Lan, Hengyi Liang, Xiangguo Liu, Yixuan Wang
Safety-Assured Design and Adaptation of Learning-Enabled Autonomous Systems. 753-760
8D: Emerging Hardware Verification
- Muhammad Hassan, Daniel Große, Rolf Drechsler
System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations. 761-766 - Lukas Burgholzer
Random Stimuli Generation for the Verification of Quantum Circuits. 767-772 - Chrysostomos Chatzigeorgiou, Dimitrios Garyfallou
Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models. 773-778
8E: Optimization and Mapping Methods for Quantum Technologies
- Eleonora Testa, Siang-Yun Lee, Heinz Riener, Giovanni De Micheli:
Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits. 779-785 - Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita:
Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures. 786-791 - Stefan Hillmich
Exploiting Quantum Teleportation in Quantum Circuit Mapping. 792-797
9B: Emerging System Architectures for Edge-AI
- Chuxi Li, Xiaoya Fan, Shengbing Zhang, Zhao Yang, Miao Wang, Danghui Wang, Meng Zhang:
Hardware-Aware NAS Framework with Layer Adaptive Scheduling on Embedded System. 798-805 - Robert Guirado
Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package. 806-812 - Yifan He, Jinshan Yue, Yongpan Liu, Huazhong Yang:
Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules. 813-818 - Seyed Morteza Nabavinejad, Sherief Reda, Masoumeh Ebrahimi:
BatchSizer: Power-Performance Trade-off for DNN Inference. 819-824
9C: Cutting-Edge EDA Techniques for Advanced Process Technologies
- Yibo Lin:
Deep Learning for Mask Synthesis and Verification: A Survey. 825-832 - Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, Yibo Lin, Bei Yu:
Physical Synthesis for Advanced Neural Network Processors. 833-840 - Wenjian Yu, Mingye Song, Ming Yang:
Advancements and Challenges on Parasitic Extraction for Advanced Process Technologies. 841-846
9D: Robust and Reliable Memory Centric Computing at Post-Moore
- Hanbo Sun, Zhenhua Zhu, Yi Cai, Shulin Zeng, Kaizhong Qiu, Yu Wang, Huazhong Yang:
Reliability-Aware Training and Performance Modeling for Processing-In-Memory Systems. 847-852 - Grace Li Zhang
Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks. 853-858 - Zheyu Yan
Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search. 859-864 - Tianhao Shen, Di Gao, Li Zhang, Jishen Zhao, Cheng Zhuo:
A Physical-Aware Framework for Memory Network Design Space Exploration. 865-871
9E: Design for Manufacturing and Soft Error Tolerance
- Yu-Jin Xie, Kuan-Yu Chen, Wai-Kei Mak:
Manufacturing-Aware Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement Refinement. 872-877 - Ting Liu, Yuzhuo Fu, Yan Zhang, Bin Shi:
A Hierarchical Assessment Strategy on Soft Error Propagation in Deep Learning Controller. 878-884 - Haoyu Yang, Shifan Zhang, Kang Liu, Siting Liu, Benjamin Tan
Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method. 885-891 - Zhengqi Gao, Zihao Chen, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng:
Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits. 892-897 - Tinghuan Chen
Analog IC Aging-induced Degradation Estimation via Heterogeneous Graph Convolutional Networks. 898-903
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