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M. B. Srinivas
Mandalika B. Srinivas – Srinivas B. Mandalika – Srinivas Bala Mandalika
Person information
- affiliation: BML Munjal University, Gurgaon, India
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2020 – today
- 2024
- [c102]Harshiv Chandra
, Akash Ghosh, Rahul Singh, M. B. Srinivas:
SNN-LIF Model for Glaucoma Classification. AICAS 2024: 114-118 - [c101]Sesibhushana Rao Bommana, Sreehari Veeramachaneni, M. B. Srinivas:
Bistable Physically Unclonable Function with Dynamic Threshold Voltage. MWSCAS 2024: 167-172 - 2023
- [j22]Khushi Gupta, Arshdeep Singh, Sreenivasa Reddy Yeduri, M. B. Srinivas, Linga Reddy Cenkeramaddi
Hand gestures recognition using edge computing system based on vision transformer and lightweight CNN. J. Ambient Intell. Humaniz. Comput. 14(3): 2601-2615 (2023) - 2022
- [j21]Diyanesh Chinnakkonda
Architecture slack exploitation for phase classification and performance estimation in server-class processors. J. Parallel Distributed Comput. 169: 157-170 (2022) - [j20]P. Sai Phaneendra, Chetan Vudadha, M. B. Srinivas:
Optimization of Reversible Circuits Using Gate Pair Classification. SN Comput. Sci. 3(1): 40 (2022) - [j19]Saravanan Sethuraman
Techniques to Improve Write and Retention Reliability of STT-MRAM Memory Subsystem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 2901-2914 (2022) - [j18]Mahesh Kumar Adimulam
A 12-bit, 1.1-GS/s, Low-Power Flash ADC. IEEE Trans. Very Large Scale Integr. Syst. 30(3): 277-290 (2022) - 2021
- [j17]Himanshu Thapliyal
Consumer Technology-Based Solutions for COVID-19. IEEE Consumer Electron. Mag. 10(2): 64-65 (2021) - [c100]Jyoti Bhatia, Aveen Dayal, Ajit Jha, Santosh Kumar Vishvakarma, Soumya J.
Object Classification Technique for mmWave FMCW Radars using Range-FFT Features. COMSNETS 2021: 111-115 - [c99]Kotturi Venkata SaiTeja, Ponduru Manoj Kumar, Punnamraju Sarath Chandra, N. K. Jisy
'Glaucoma - Automating the Cup-to-Disc Ratio Estimation in Fundus Images by Combining Random Walk Algorithm with Otsu Thresholding'. NER 2021: 154-157 - 2020
- [j16]Saravanan Sethuraman
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4635-4644 (2020) - [j15]Veeresh Babu Vulligaddala
A 7-Cell, Stackable, Li-Ion Monitoring and Active/Passive Balancing IC With In-Built Cell Balancing Switches for Electric and Hybrid Vehicles. IEEE Trans. Ind. Informatics 16(5): 3335-3344 (2020)
2010 – 2019
- 2019
- [j14]Goutham Makkena
Levin's Transformation-based Continuous-Time Linear-Phase Selective Filters. Circuits Syst. Signal Process. 38(11): 4905-4920 (2019) - [j13]Avinash S. Vaidya
A frequency domain beamspace adaptive receive beamformer for ultrasound imaging systems: phantom simulation results. Signal Image Video Process. 13(3): 591-599 (2019) - [j12]Syed Ershad Ahmed
An Improved Logarithmic Multiplier for Media Processing. J. Signal Process. Syst. 91(6): 561-574 (2019) - 2018
- [j11]Goutham Makkena, M. B. Srinivas:
Nonlinear Sequence Transformation-Based Continuous-Time Wavelet Filter Approximation. Circuits Syst. Signal Process. 37(3): 965-983 (2018) - [j10]Syed Ershad Ahmed, Ch. Santosh Varma, M. B. Srinivas:
Improved designs of digit-by-digit decimal multiplier. Integr. 61: 150-159 (2018) - [j9]Veeresh Babu Vulligaddala
A Digitally Calibrated Bandgap Reference With 0.06% Error for Low-Side Current Sensing Application. IEEE J. Solid State Circuits 53(10): 2951-2957 (2018) - [j8]Chetan Vudadha, Sai Phaneendra Parlapalli, M. B. Srinivas:
Energy efficient design of CNFET-based multi-digit ternary adders. Microelectron. J. 75: 75-86 (2018) - [j7]Chetan Vudadha
Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4313-4325 (2018) - [c98]Linga Reddy Cenkeramaddi
Design of Software and Data Analytics for Self-Powered Wireless IoT Devices. iSES 2018: 118-123 - [c97]Chetan Vudadha, M. B. Srinivas:
Design Methodologies for Ternary Logic Circuits. ISMVL 2018: 192-197 - [c96]Mahesh Kumar Adimulam, Amit Kapoor, Sreehari Veeramachaneni
An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications. VLSID 2018: 19-24 - 2017
- [c95]Mahesh Kumar Adimulam, Adimulam Divya, K. Tejaswi, M. B. Srinivas:
A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements. EMBC 2017: 3844-3847 - [c94]Mahesh Kumar Adimulam, Krishna Kumar Movva, K. Kolluru, M. B. Srinivas:
A 0.32 µW, 76.8 dB SNDR Programmable Gain Instrumentation Amplifier for Bio-Potential Signal Processing Applications. ISVLSI 2017: 655-660 - [c93]Mahesh Kumar Adimulam, M. B. Srinivas:
Ultra Low Power Programmable Wireless ExG SoC Design for IoT Healthcare System. MobiHealth 2017: 41-49 - [c92]Sai Phaneendra Parlapalli, Chetan Vudadha, M. B. Srinivas:
Optimizing the Reversible Circuits Using Complementary Control Line Transformation. RC 2017: 111-126 - [c91]Sai Phaneendra Parlapalli, Chetan Vudadha, M. B. Srinivas:
An ESOP Based Cube Decomposition Technique for Reversible Circuits. RC 2017: 127-140 - [c90]M. B. Srinivas:
T2A: Analog and RF circuits. SoCC 2017: 1 - [c89]Mahesh Kumar Adimulam, Krishna Kumar Movva, M. B. Srinivas:
A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications. SoCC 2017: 45-50 - [c88]Mahesh Kumar Adimulam, Krishna Kumar Movva, Amit Kapoor, M. B. Srinivas:
A low power, programmable bias inverter quantizer (BIQ) flash ADC. VLSI-SoC 2017: 1-6 - [c87]Anjali Gopinath, Ravi Kumar Adusumalli, Veeresh Babu Vulligaddala, M. B. Srinivas:
A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range without Using a Rail-to-Rail Op-Amp. VLSID 2017: 329-334 - 2016
- [j6]Rakhee
A Soft Computing Approach for Data Routing in Hospital Area Networks (HAN). Int. J. Bus. Data Commun. Netw. 12(2): 16-27 (2016) - [c86]Syed Ershad Ahmed, Sanket Kadam, M. B. Srinivas:
An Iterative Logarithmic Multiplier with Improved Precision. ARITH 2016: 104-111 - [c85]Mahesh Kumar Adimulam, M. B. Srinivas:
Modeling of EXG (ECG, EMG and EEG) non-idealities using MATLAB. CISP-BMEI 2016: 1584-1589 - [c84]Chetan Vudadha, P. Sai Phaneendra, M. B. Srinivas:
An Efficient Design Methodology for CNFET Based Ternary Logic Circuits. iNIS 2016: 278-283 - [c83]Syed Ershad Ahmed, S. Sweekruth Srinivas, M. B. Srinivas:
A Hybrid Energy Efficient Digital Comparator. VLSID 2016: 567-568 - 2014
- [c82]Soumya Ganguly, Abhishek Mittal, Syed Ershad Ahmed, M. B. Srinivas:
A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits. APCCAS 2014: 69-72 - [c81]Avinash S. Vaidya
Estimation of Arterial Stiffness through Pulse Transit Time Measurement. BIODEVICES 2014: 238-242 - [c80]Subhankar Pal
A New Design of an N-Bit Reversible Arithmetic Logic Unit. ISED 2014: 224-225 - [c79]Abhilash K. N, M. B. Srinivas:
A reconfigurable 0-L1-L2 S-MASH2 modulator with high-level sizing and power estimation. SoCC 2014: 347-352 - [c78]B. Naveen Kumar Reddy, M. Chandra Sekhar, Sreehari Veeramachaneni
A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units. VLSID 2014: 128-132 - [c77]Ch. Santosh Varma, Syed Ershad Ahmed, M. B. Srinivas:
A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter. VLSID 2014: 365-368 - [c76]P. Sai Phaneendra
An Optimized Design of Reversible Quantum Comparator. VLSID 2014: 557-562 - 2013
- [c75]Goutham Makkena, Prabhakara Rao, M. B. Srinivas:
Uniform approximation of Gaussian wavelet for biomedical signal processing in analog domain. EMBC 2013: 2886-2889 - [c74]Avinash S. Vaidya
A smart phone/tablet based mobile health care system for developing countries. EMBC 2013: 4642-4645 - 2012
- [c73]Santosh Kumar Jena, M. B. Srinivas:
On the Suitability of Multi-Core Processing for Embedded Automotive Systems. CyberC 2012: 315-322 - [c72]Chetan Vudadha, Phaneendra P. Sai
CNFET based ternary magnitude comparator. ISCIT 2012: 942-946 - [c71]Syed Ershad Ahmed, Sibi Abraham, Sreehari Veeramachaneni
A Modified Twin Precision Multiplier with 2D Bypassing Technique. ISED 2012: 102-106 - [c70]Chetan Vudadha, P. Sai Phaneendra
Design of Prefix-Based Optimal Reversible Comparator. ISVLSI 2012: 201-206 - [c69]Chetan Vudadha, P. Sai Phaneendra
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. ISVLSI 2012: 225-230 - [c68]Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design 2012: 280-285 - 2011
- [c67]Chetan Kumar V., P. Sai Phaneendra
A Unified Architecture for BCD and Binary Adder/Subtractor. DSD 2011: 426-429 - [c66]P. Sai Phaneendra
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. ISCIT 2011: 472-477 - [c65]Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni
A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter. ISED 2011: 24-29 - [c64]Chetan Kumar V., P. Sai Phaneendra
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. ISED 2011: 100-105 - [c63]Chetan Kumar V., Sai Phaneendra P.
A Prefix Based Reconfigurable Adder. ISVLSI 2011: 349-350 - 2010
- [j5]Sandeep Saini
An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. J. Low Power Electron. 6(3): 429-435 (2010) - [c62]Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni
Low power, variable resolution pipelined analog to Digital converter with sub flash architecture. APCCAS 2010: 204-207 - [c61]Sandeep Saini
Implementation of low power FFT structure using a method based on conditionally coded blocks. APCCAS 2010: 935-938 - [c60]Gudipati Kalyan, M. B. Srinivas:
An efficient ODT calibration scheme for improved signal integrity in memory interface. APCCAS 2010: 1211-1214 - [c59]Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni
A low power, variable resolution two-step flash ADC. ACM Great Lakes Symposium on VLSI 2010: 39-44 - [c58]Pradeep Jamwal, M. B. Srinivas, G. V. K. Sarma, M. Murali Krishna:
A new approach to minimize leakage power in nano-scale VLSI adder. ICWET 2010: 880-886 - [c57]Vasanth Iyer
Effects of channel SNR in mobile cognitive radios and coexisting deployment of cognitive wireless sensor networks. IPCCC 2010: 294-301 - [c56]Mahesh Kumar Adimulam, Sreehari Veeramachaneni
A Novel, Variable Resolution Flash ADC with Sub Flash Architecture. ISVLSI 2010: 434-435 - [c55]Sandeep Saini
An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. VLSI Design 2010: 411-416
2000 – 2009
- 2009
- [j4]Mahesh Kumar Adimulam, Sreehari Veeramachaneni
A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter. J. Low Power Electron. 5(3): 279-290 (2009) - [j3]Himanshu Thapliyal
Efficient Reversible Logic Design of BCD Subtractors. Trans. Comput. Sci. 3: 99-121 (2009) - [c54]Abinesh Ramachandran, Bharghava Rajaram, Mandalika B. Srinivas:
Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial Communication. ISVLSI 2009: 103-108 - [c53]Anshul Singh, Aman Gupta, Sreehari Veeramachaneni
A High Performance Unified BCD and Binary Adder/Subtractor. ISVLSI 2009: 211-216 - [c52]Swathi Ramasahayam, M. B. Srinivas:
All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex. ISVLSI 2009: 258-262 - [c51]Vasanth Iyer
Multi-hop scheduling and local data link aggregation dependant Qos in modeling and simulation of power-aware wireless sensor networks. IWCMC 2009: 844-848 - [c50]Mahesh Kumar Adimulam, Sreehari Veeramachaneni
A novel low power, variable resolution pipelined ADC. SoCC 2009: 183-186 - [c49]Sreehari Veeramachaneni
Design of a Low Power, Variable-Resolution Flash ADC. VLSI Design 2009: 117-122 - 2008
- [c48]J. V. R. Ravindra, M. B. Srinivas:
Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits. ACM Great Lakes Symposium on VLSI 2008: 111-114 - [c47]Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas:
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. ISQED 2008: 43-46 - [c46]Lingamneni Avinash, Kirthi Krishna Muntimadugu, M. B. Srinivas:
A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection. ISVLSI 2008: 128-133 - [c45]Vasanth Iyer
Training Data Compression Algorithms and Reliability in Large Wireless Sensor Networks. SUTC 2008: 480-485 - [c44]Sreehari Veeramachaneni
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. VLSI Design 2008: 547-552 - 2007
- [j2]J. V. R. Ravindra, M. B. Srinivas:
Delay and Energy Efficient Coding Techniques for Capacitive Interconnects. J. Circuits Syst. Comput. 16(6): 929-942 (2007) - [j1]M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas:
New and Improved Architectures for Montgomery Modular Multiplication. Mob. Networks Appl. 12(4): 281-291 (2007) - [c43]J. V. R. Ravindra, M. B. Srinivas:
A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. DSD 2007: 325-330 - [c42]Keerthi Laal Kala, M. B. Srinivas:
Rule Selection in Fuzzy Systems using Heuristics and Branch Prediction. FOCI 2007: 603-607 - [c41]Shashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas:
Area Efficient High Speed Architecture of Bruun's FFT for Software Defined Radio. GLOBECOM 2007: 3118-3122 - [c40]Sreehari Veeramachaneni
Novel architectures for efficient (m, n) parallel counters. ACM Great Lakes Symposium on VLSI 2007: 188-191 - [c39]Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas:
Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects. ACM Great Lakes Symposium on VLSI 2007: 371-376 - [c38]Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas:
Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN). ISCAS 2007: 1129-1132 - [c37]Sreehari Veeramachaneni
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks. ISCAS 2007: 3271-3274 - [c36]Sreehari Veeramachaneni
Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. ISVLSI 2007: 343-350 - [c35]K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas:
Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme. ISVLSI 2007: 401-408 - [c34]J. V. R. Ravindra, M. B. Srinivas:
Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs. Nano-Net 2007: 25 - [c33]Shashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas:
A Comparative Study of Different FFT Architectures for Software Defined Radio. SAMOS 2007: 375-384 - [c32]Sudhakar Maddi, M. B. Srinivas:
A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA. SBCCI 2007: 147-152 - [c31]K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas:
Bus encoding schemes for minimizing delay in VLSI interconnects. SBCCI 2007: 184-189 - [c30]J. V. R. Ravindra, Srinivas Bala Mandalika:
Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach. SBCCI 2007: 207-211 - [c29]M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas:
A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC. VLSI-SoC 2007: 252-257 - [c28]Sreehari Veeramachaneni
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. VLSI Design 2007: 324-329 - [c27]M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas:
A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n). VLSI Design 2007: 750-755 - 2006
- [c26]Himanshu Thapliyal
The New BCD Subtractor and Its Reversible Logic Implementation. Asia-Pacific Computer Systems Architecture Conference 2006: 466-472 - [c25]Himanshu Thapliyal
Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture. AICCSA 2006: 88-92 - [c24]Himanshu Thapliyal
Novel Reversible Multiplier Architecture Using Reversible TSG Gate. AICCSA 2006: 100-103 - [c23]Keerthi Laal Kala, M. B. Srinivas:
A Generic Architecture for Intelligent System Hardware. APCCAS 2006: 321-326 - [c22]Pallavi Devi Gopineedi, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations. ESA 2006: 160-168 - [c21]K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas:
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method. DELTA 2006: 336-339 - [c20]Himanshu Thapliyal
Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder. DELTA 2006: 414-417 - [c19]Ramachandruni Venkata Kamala, M. Sudhakar, M. B. Srinivas:
An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n). DSD 2006: 155-159 - [c18]K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas:
A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects. ISCAS 2006 - [c17]Ramachandruni Venkata Kamala, M. B. Srinivas:
High-Throughput Montgomery Modular Multiplication. VLSI-SoC 2006: 58-62 - [c16]Himanshu Thapliyal
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. VLSI Design 2006: 387-392 - [i7]Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas:
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. CoRR abs/cs/0603088 (2006) - [i6]Himanshu Thapliyal, M. B. Srinivas:
A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits. CoRR abs/cs/0603091 (2006) - [i5]Himanshu Thapliyal, M. B. Srinivas:
An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates. CoRR abs/cs/0603092 (2006) - [i4]Himanshu Thapliyal, M. B. Srinivas:
Novel Reversible Multiplier Architecture Using Reversible TSG Gate. CoRR abs/cs/0605004 (2006) - [i3]Himanshu Thapliyal, M. B. Srinivas:
Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU. CoRR abs/cs/0609023 (2006) - [i2]Himanshu Thapliyal, M. B. Srinivas:
VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics. CoRR abs/cs/0609028 (2006) - [i1]Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas:
Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format. CoRR abs/cs/0609036 (2006) - 2005
- [c15]Himanshu Thapliyal
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. Asia-Pacific Computer Systems Architecture Conference 2005: 805-817 - [c14]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture. AMCS 2005: 72-76 - [c13]Himanshu Thapliyal, M. B. Srinivas, Rameshwar Rao, Hamid R. Arabnia:
Verilog Coding Style for Efficient Synthesis In FPGA. CDES 2005: 85-90 - [c12]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
Design for A Fast And Low Power 2's Complement Multiplier. CDES 2005: 165-167 - [c11]Saurabh Kotiyal, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison. CSC 2005: 74-77 - [c10]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor. ESA 2005: 60-68 - [c9]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs. ESA 2005: 106-116 - [c8]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
Reversible Logic Synthesis of Half, Full and Parallel Subtractors. ESA 2005: 165-181 - [c7]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier. Security and Management 2005: 40-44 - [c6]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
Implementation of A Fast Square In RSA Encryption/Decryption Architecture. Security and Management 2005: 371-374 - [c5]K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas:
A novel deep submicron low power bus coding technique. Circuits, Signals, and Systems 2005: 154-159 - [c4]Keerthi Laal Kala, M. B. Srinivas:
A 32-Bit Binary Floating Point Neuro-Chip. ICNC (3) 2005: 1015-1021 - [c3]Yaswanth Narvaneni, M. B. Srinivas:
Local Language Support for Handheld Devices. ITCC (2) 2005: 799-800 - 2003
- [c2]K. Kalyan Chakravarthy, M. B. Srinivas:
Speech encoding and encryption in VLSI. ASP-DAC 2003: 569-570 - [c1]I. Vijay Kumar, M. B. Srinivas:
Design of a digital CDMA receiver. ASP-DAC 2003: 587-588
Coauthor Index
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