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An Improved Logarithmic Multiplier for Media Processing

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Abstract

As the modern computing systems become increasingly embedded and portable, a growing set of applications in media processing (graphics, audio, video, and image) has evolved. Multiplication is the operation that is most often used in these applications which when accomplished in logarithmic number system results in an area efficient and faster design. In this work, the authors describe a technique that combines Mitchell’s approximation with a novel hardware truncation scheme resulting in an iterative multiplier with improved precision and reduced area. Further, a new fractional predictor combined with an existing truncated logarithmic shifter significantly reduces the overall hardware cost of the multiplier. Simulations carried out on benchmark image processing applications such as Lena, cameraman and pirate clearly indicate that the proposed technique performs better than those available in the literature.

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References

  1. Palem, K.V. (2005). Energy aware computing through probabilistic switching: A study of limits. IEEE Transactions on Computers, 54(9), 1123–1137. https://doi.org/10.1109/TC.2005.145.

    Article  Google Scholar 

  2. Mitchell, J.N. (1962). Computer multiplication and division using binary logarithms. IRE Transactions on Electronic Computers, EC-11(4), 512–517.

    Article  MathSciNet  MATH  Google Scholar 

  3. Paliouras, V., & Stouraitis, T. (2001). Low-power properties of the logarithmic number system. In Proceedings of the 15th IEEE Symposium on Computer Arithmetic, (Vol. 2001 pp. 229–236).

  4. Babic, Z., Avramovic, A., & Bulic, P. (2011). An iterative logarithmic multiplier. Microprocessors and Microsystems, 35(1), 23–33.

    Article  Google Scholar 

  5. Sullivan, M., & Swartzlander, E. (2012). Truncated error correction for flexible approximate multiplication. In 2012 Conference Record of the Forty Sixth Asilomar Conference on Signals, Systems and Computers (ASILOMAR) (pp. 355–359).

  6. Abed, K., & Siferd, R. (2003). Cmos vlsi implementation of a low-power logarithmic converter. IEEE Transactions on Computers, 52(11), 1421–1433.

    Article  Google Scholar 

  7. Abed, K. (2003). Vlsi implementation of a low-power antilogarithmic converter. IEEE Transactions on Computers, 52(9), 1221–1228.

    Article  Google Scholar 

  8. Combet, M., Van Zonneveld, H., & Verbeek, L. (1965). Computation of the base two logarithm of binary numbers. IEEE Transactions on Electronic Computers, EC-14(6), 863–867.

    Article  Google Scholar 

  9. Hall, E.L., Lynch, D., & Dwyer, I.S.J. (1970). Generation of products and quotients using approximate binary logarithms for digital filtering applications. IEEE Transactions on Computers, C-19(2), 97–105.

    Article  MATH  Google Scholar 

  10. SanGregory, S., Brothers, C., Gallagher, D., & Siferd, R. (1999). A fast, low-power logarithm approximation with cmos vlsi implementation. In 1999 42nd Midwest Symposium on Circuits and Systems, (Vol. 1 pp. 388–391).

  11. Mahalingam, V., & Ranganathan, N. (2006). Improving accuracy in mitchell’s logarithmic multiplication using operand decomposition. IEEE Transactions on Computers, 55(12), 1523–1535.

    Article  Google Scholar 

  12. Brubaker, T., & Becker, J. (1975). Multiplication using logarithms implemented with read-only memory. IEEE Transactions on Computers, C-24(8), 761–765.

    Article  MATH  Google Scholar 

  13. Mclaren, D. (2003). Improved mitchell-based logarithmic multiplier for low-power dsp applications. In 2003 Proceedings of the IEEE International [Systems-on-Chip] on SOC Conference (pp. 53–56).

  14. Sullivan, M., & Swartzlander, E. (2013). Truncated logarithmic approximation. In 2013 21st IEEE Symposium on Computer Arithmetic (ARITH) (pp. 191–198).

  15. Gupta, V., Mohapatra, D., Park, S.P., Raghunathan, A., & Roy, K. (2011). Impact: imprecise adders for low-power approximate computing. In Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design (pp. 409–414): IEEE Press.

  16. Lau, M.S., Ling, K.-V., & Chu, Y.-C. (2009). Energy-aware probabilistic multiplier: design and analysis. In Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, ser. CASES ’09. New York, NY, USA: ACM (pp. 281–290). https://doi.org/10.1145/1629395.1629434

  17. Gonzalez, R.C., & Wood, R.E. Digital image processing, 2nd Edition, Prentice-Hall.

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Authors and Affiliations

  1. Electrical Department, BITS Pilani, Hyderabad Campus, Hyderabad, India

    Syed Ershad Ahmed

  2. School of Engineering and Technology, BML Munjal University, Gurgaon, India

    M. B. Srinivas

Authors
  1. Syed Ershad Ahmed
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  2. M. B. Srinivas
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Correspondence to Syed Ershad Ahmed.

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Ahmed, S.E., Srinivas, M.B. An Improved Logarithmic Multiplier for Media Processing. J Sign Process Syst 91, 561–574 (2019). https://doi.org/10.1007/s11265-018-1350-2

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  • DOI: https://doi.org/10.1007/s11265-018-1350-2

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