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T. Venkata Kalyan
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2020 – today
- 2024
- [c8]Praseetha M
, Madhu Mutyam
Cache Line Pinning for Mitigating Row Hammer Attack. ICPP 2024: 802-811 - 2023
- [i1]Rohith Krishnan S, Venkata Kalyan Tavva, Rupesh Nasre:
A Graph Data Structure to Optimize Dynamic Graph Processing on GPUs. CoRR abs/2306.08252 (2023) - 2022
- [j4]Saravanan Sethuraman
Techniques to Improve Write and Retention Reliability of STT-MRAM Memory Subsystem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 2901-2914 (2022) - 2020
- [j3]Saravanan Sethuraman
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4635-4644 (2020) - [j2]Praveen Alapati
A Scalable and Energy-Efficient Concurrent Binary Search Tree With Fatnodes. IEEE Trans. Sustain. Comput. 5(4): 468-484 (2020)
2010 – 2019
- 2017
- [c7]Praveen Alapati, Venkata Kalyan Tavva
FatCBST: Concurrent Binary Search Tree with Fatnodes. HPCC/SmartCity/DSS 2017: 356-363 - 2014
- [j1]Venkata Kalyan Tavva
EFGR: An Enhanced Fine Granularity Refresh Feature for High-Performance DDR4 DRAM Devices. ACM Trans. Archit. Code Optim. 11(3): 31:1-31:26 (2014) - [c6]Sudharsan Jagathrakshakan, Venkata Kalyan Tavva, Madhu Mutyam
Data remapping for an energy efficient burst chop in DRAM memory systems. PACT 2014: 507-508 - [c5]T. Venkata Kalyan
Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time. ASP-DAC 2014: 598-603 - [c4]Pritam Majumder, T. Venkata Kalyan
SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache. ICCD 2014: 104-109 - 2012
- [c3]C. J. Janraj, T. Venkata Kalyan
Way Sharing Set Associative Cache Architecture. VLSI Design 2012: 251-256
2000 – 2009
- 2008
- [c2]T. Venkata Kalyan
Word-interleaved cache: an energy efficient data cache architecture. ISLPED 2008: 265-270 - [c1]T. Venkata Kalyan
Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design. VLSI Design 2008: 235-241
Coauthor Index
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