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An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems

Published: 05 June 2016 Publication History

Abstract

Emerging technologies provide SoCs with fine-grained DVFS capabilities both in space (number of domains) and time (transients in the order of tens of nanoseconds). Analyzing these systems requires cycle-accurate accounting of rapidly-changing dynamics and complex interactions among accelerators, interconnect, memory, and OS. We present an FPGA-based infrastructure that facilitates such analyses for high-performance embedded systems. We show how our infrastructure can be used to first generate SoCs with loosely-coupled accelerators, and then perform design-space exploration considering several DVFS policies under full-system workload scenarios, sweeping spatial and temporal domain granularity.

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Cited By

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  • (2024)BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00063(801-817)Online publication date: 29-Jun-2024
  • (2024)Accelerator Design with High-Level SynthesisHandbook of Computer Architecture10.1007/978-981-97-9314-3_19(841-873)Online publication date: 21-Dec-2024
  • (2023)Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323678(1-9)Online publication date: 28-Oct-2023
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cover image ACM Other conferences
DAC '16: Proceedings of the 53rd Annual Design Automation Conference
June 2016
1048 pages
ISBN:9781450342360
DOI:10.1145/2897937
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 05 June 2016

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Cited By

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  • (2024)BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00063(801-817)Online publication date: 29-Jun-2024
  • (2024)Accelerator Design with High-Level SynthesisHandbook of Computer Architecture10.1007/978-981-97-9314-3_19(841-873)Online publication date: 21-Dec-2024
  • (2023)Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323678(1-9)Online publication date: 28-Oct-2023
  • (2022)Dynamically-Tunable Dataflow Architectures Based on Markov Queuing ModelsElectronics10.3390/electronics1104055511:4(555)Online publication date: 12-Feb-2022
  • (2022)An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core ProcessorsACM Transactions on Architecture and Code Optimization10.1145/351682519:3(1-24)Online publication date: 4-May-2022
  • (2022)Accelerator Design with High-Level SynthesisHandbook of Computer Architecture10.1007/978-981-15-6401-7_19-1(1-33)Online publication date: 27-Jan-2022
  • (2021)CICERO: A Domain-Specific Architecture for Efficient Regular Expression MatchingACM Transactions on Embedded Computing Systems10.1145/347698220:5s(1-24)Online publication date: 17-Sep-2021
  • (2021)Evaluation of Tradeoffs in the Design of FPGA Fabrics Using Electrostrictive 2-D FETsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.305997929:4(691-701)Online publication date: Apr-2021
  • (2020)ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116317(1049-1054)Online publication date: Mar-2020
  • (2020)BYOCProceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3373376.3378479(699-714)Online publication date: 9-Mar-2020
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