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Farhad Merchant
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2020 – today
- 2024
- [j12]Chandan Kumar Jha
, Khushboo Qayyum
veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 4169-4179 (2024) - [c48]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. ASPDAC 2024: 282-287 - [c47]Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn:
Error Detection and Correction Codes for Safe In-Memory Computations. ETS 2024: 1-4 - [c46]Gokulnath Rajendran, Furqan Zahoor, Sidhaant Sachin Thakker
Harnessing Entropy: RRAM Crossbar-based Unified PUF and RNG. VLSID 2024: 560-564 - [c45]Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. VLSID 2024: 565-570 - [i32]Lennart M. Reimann, Anschul Prashar, Chiara Ghinami, Rebecca Pelke, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL. CoRR abs/2401.17819 (2024) - [i31]Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn:
Error Detection and Correction Codes for Safe In-Memory Computations. CoRR abs/2404.09818 (2024) - [i30]Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant:
In-Memory Mirroring: Cloning Without Reading. CoRR abs/2407.02921 (2024) - [i29]Simranjeet Singh, Farhad Merchant, Sachin B. Patkar:
Resistive Memory for Computing and Security: Algorithms, Architectures, and Platforms. CoRR abs/2407.03843 (2024) - 2023
- [j11]Simranjeet Singh
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. IEEE Embed. Syst. Lett. 15(4): 230-233 (2023) - [j10]Niraj N. Sharma
CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism. J. Syst. Archit. 135: 102801 (2023) - [j9]Anouar Nechi
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing? ACM Trans. Reconfigurable Technol. Syst. 16(4): 60:1-60:32 (2023) - [c44]Simranjeet Singh
Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs. ASP-DAC 2023: 449-454 - [c43]Anand Raj, Nikhitha Avula, Pabitra Das
DeepAttack: A Deep Learning Based Oracle-less Attack on Logic Locking. ISCAS 2023: 1-5 - [c42]Omar Ghazal, Simranjeet Singh
IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines. ISLPED 2023: 1-6 - [c41]Simranjeet Singh
Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies. NANOARCH 2023: 30:1-30:7 - [c40]Elmira Moussavi, Animesh Singh, Dominik Sisejkovic, Aravind Padma Kumar, Daniyar Kizatov, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri
Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. NEWCAS 2023: 1-5 - [c39]Simranjeet Singh
Finite State Automata Design using 1T1R ReRAM Crossbar. NEWCAS 2023: 1-5 - [c38]Simranjeet Singh
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar. NEWCAS 2023: 1-5 - [c37]Gokulnath Rajendran, Furqan Zahoor, Simranjeet Singh
PR-PUF: A Reconfigurable Strong RRAM PUF. VLSI-SoC 2023: 1-6 - [c36]Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. VLSI-SoC 2023: 1-6 - [i28]Elmira Moussavi, Animesh Singh, Dominik Sisejkovic, Aravind Padma Kumar, Daniyar Kizatov, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri
Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. CoRR abs/2304.05686 (2023) - [i27]Simranjeet Singh
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar. CoRR abs/2304.13531 (2023) - [i26]Simranjeet Singh
Finite State Automata Design using 1T1R ReRAM Crossbar. CoRR abs/2304.13552 (2023) - [i25]Omar Ghazal, Simranjeet Singh, Tousif Rahman, Shengqi Yu, Yujin Zheng, Domenico Balsamo, Sachin B. Patkar, Farhad Merchant, Fei Xia, Alex Yakovlev, Rishad A. Shafik:
IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines. CoRR abs/2305.12914 (2023) - [i24]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. CoRR abs/2307.03669 (2023) - [i23]Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. CoRR abs/2308.02694 (2023) - [i22]Simranjeet Singh
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. CoRR abs/2309.04868 (2023) - [i21]Ankit Bende, Simranjeet Singh
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. CoRR abs/2310.10460 (2023) - 2022
- [j8]Felix Staudigl
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security. IEEE Des. Test 39(2): 90-99 (2022) - [j7]Dominik Sisejkovic
Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1716-1729 (2022) - [c35]Melvin Galicia, Stephan Menzel, Farhad Merchant, Maximilian Müller, Hsin-Yu Chen, Qing-Tai Zhao, Felix Cüppers, Abdur R. Jalil
NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future. DATE 2022: 957-962 - [c34]Felix Staudigl, Hazem Al Indari, Daniel Schön
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. DATE 2022: 1181-1184 - [c33]Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu
pHGen: A pH-Based Key Generation Mechanism Using ISFETs. HOST 2022: 61-64 - [c32]Melvin Galicia, Farhad Merchant, Rainer Leupers:
A Parallel SystemC Virtual Platform for Neuromorphic Architectures. ISQED 2022: 1-6 - [c31]Michael Gansen, Jie Lou, Florian Freye
Discrete Steps towards Approximate Computing. ISQED 2022: 1-6 - [c30]Farhad Merchant:
Security as an Important Ingredient in Neuromorphic Engineering. ISVLSI 2022: 314-319 - [c29]Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. LATS 2022: 1-4 - [c28]Simranjeet Singh
PA-PUF: A Novel Priority Arbiter PUF. VLSI-SoC 2022: 1-6 - [i20]Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant:
pHGen: A pH-Based Key Generation Mechanism Using ISFETs. CoRR abs/2202.12085 (2022) - [i19]Simranjeet Singh, Srinivasu Bodapati, Sachin B. Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant:
PA-PUF: A Novel Priority Arbiter PUF. CoRR abs/2207.10526 (2022) - [i18]Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. CoRR abs/2208.04769 (2022) - [i17]Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant:
Hardware Security Primitives using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs. CoRR abs/2211.03526 (2022) - 2021
- [j6]Suresh Nambi
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems. IEEE Access 9: 103691-103708 (2021) - [j5]Dominik Sisejkovic
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. ACM J. Emerg. Technol. Comput. Syst. 17(3): 30:1-30:26 (2021) - [c27]Ilia Polian, Frank Altmann
Nano Security: From Nano-Electronics to Secure Systems. DATE 2021: 1334-1339 - [c26]Shubham Rai
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? DATE 2021: 1905-1914 - [c25]Lennart M. Reimann
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. ICCD 2021: 603-607 - [c24]Vinay Saxena, Ankitha Reddy, Jonathan Neudorfer, John L. Gustafson, Sangeeth Nambiar, Rainer Leupers, Farhad Merchant:
Brightening the Optical Flow through Posit Arithmetic. ISQED 2021: 463-468 - [c23]Dominik Sisejkovic
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. VLSI-SoC 2021: 1-6 - [c22]Farhad Merchant, Dominik Sisejkovic
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. VLSID 2021: 270-275 - [c21]Ihsen Alouani
An Investigation on Inherent Robustness of Posit Data Representation. VLSID 2021: 276-281 - [i16]Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant, Rainer Leupers:
An Investigation on Inherent Robustness of Posit Data Representation. CoRR abs/2101.01416 (2021) - [i15]Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers:
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. CoRR abs/2101.05591 (2021) - [i14]Vinay Saxena, Ankitha Reddy, Jonathan Neudorfer, John L. Gustafson, Sangeeth Nambiar, Rainer Leupers, Farhad Merchant:
Brightening the Optical Flow through Posit Arithmetic. CoRR abs/2101.06665 (2021) - [i13]Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers:
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. CoRR abs/2107.01915 (2021) - [i12]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers:
Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks. CoRR abs/2107.08695 (2021) - [i11]Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. CoRR abs/2109.02379 (2021) - [i10]Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers:
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. CoRR abs/2112.01087 (2021) - [i9]Melvin Galicia, Farhad Merchant, Rainer Leupers:
A Parallel SystemC Virtual Platform for Neuromorphic Architectures. CoRR abs/2112.13157 (2021) - 2020
- [j4]Jure Vreca
Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit. IEEE Access 8: 165913-165926 (2020) - [c20]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann
Scaling Logic Locking Schemes to Multi-module Hardware Designs. ARCS 2020: 138-152 - [c19]Andre Guntoro
Next Generation Arithmetic for Edge Computing. DATE 2020: 1357-1365 - [c18]Dominik Sisejkovic
A secure hardware-software solution based on RISC-V, logic locking and microkernel. SCOPES 2020: 62-65 - [i8]Riya Jain, Niraj N. Sharma, Farhad Merchant, Sachin B. Patkar, Rainer Leupers:
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism. CoRR abs/2006.00364 (2020) - [i7]Suresh Nambi, Salim Ullah, Aditya Lohana, Siva Satyendra Sahoo
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems. CoRR abs/2010.12869 (2020) - [i6]Dominik Sisejkovic
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. CoRR abs/2011.10389 (2020)
2010 – 2019
- 2019
- [c17]Dominik Sisejkovic
Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. ETS 2019: 1-6 - [c16]Dominik Sisejkovic
Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans. ACM Great Lakes Symposium on VLSI 2019: 27-32 - [c15]Dominik Sisejkovic
Protecting the Integrity of Processor Cores with Logic Encryption. SoCC 2019: 424-425 - [c14]Dominik Sisejkovic
A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms. VLSI-DAT 2019: 1-4 - [c13]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. VLSID 2019: 64-69 - [c12]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
Applying Modified Householder Transform to Kalman Filter. VLSID 2019: 431-436 - 2018
- [j3]Farhad Merchant
Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization. IEEE Trans. Parallel Distributed Syst. 29(8): 1707-1720 (2018) - [c11]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design. ARC 2018: 119-131 - [c10]Rohit Chaurasiya, John L. Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi
Parameterized Posit Arithmetic Hardware Generator. ICCD 2018: 334-341 - [i5]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design. CoRR abs/1802.03650 (2018) - [i4]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR abs/1803.05320 (2018) - 2017
- [j2]Farhad Merchant
Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. Parallel Process. Lett. 27(3-4): 1750006:1-1750006:17 (2017) - 2016
- [c9]Debjyoti Bhattacharjee
Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays. VLSI-SoC 2016: 1-6 - [c8]Farhad Merchant
Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation. VLSID 2016: 98-103 - [c7]Farhad Merchant
Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic. VLSID 2016: 415-420 - [i3]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design. CoRR abs/1610.06385 (2016) - [i2]Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. CoRR abs/1610.08705 (2016) - [i1]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Efficient Realization of Householder Transform through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR abs/1612.04470 (2016) - 2015
- [c6]Farhad Merchant
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. VLSID 2015: 153-158 - 2014
- [j1]Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. J. Syst. Archit. 60(7): 592-614 (2014) - [c5]Zoltán Endre Rákossy, Farhad Merchant
Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation. ASAP 2014: 188-189 - [c4]Mahesh Mahadurkar, Farhad Merchant
Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs. ICSAMOS 2014: 225-232 - [c3]Zoltán Endre Rákossy, Farhad Merchant
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation. VLSI-SoC 2014: 1-6 - [c2]Farhad Merchant
Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). VLSID 2014: 258-263 - 2011
- [c1]Alok Baluni, Farhad Merchant, S. K. Nandy, Srinivasan Balakrishnan:
A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support. ISED 2011: 45-50
Coauthor Index
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last updated on 2024-11-13 23:49 CET by the dblp team
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