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Vlad Mihai Sima
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2010 – 2019
- 2018
- [j5]Ernst Joachim Houtgast, Vlad Mihai Sima, Koen Bertels, Zaid Al-Ars:
Hardware acceleration of BWA-MEM genomic short read mapping for longer read lengths. Comput. Biol. Chem. 75: 54-64 (2018) - [c22]Ernst Joachim Houtgast, Vlad Mihai Sima, Koen Bertels, Zaid Al-Ars:
Comparative Analysis of System-Level Acceleration Techniques in Bioinformatics: A Case Study of Accelerating the Smith-Waterman Algorithm for BWA-MEM. BIBE 2018: 243-246 - 2017
- [c21]Ernst Houtgast, Vlad Mihai Sima, Zaid Al-Ars:
High Performance Streaming Smith-Waterman Implementation with Implicit Synchronization on Intel FPGA using OpenCL. BIBE 2017: 492-496 - 2016
- [j4]Ernst Joachim Houtgast, Vlad Mihai Sima, Koen Bertels, Zaid Al-Ars:
An Efficient GPUAccelerated Implementation of Genomic Short Read Mapping with BWAMEM. SIGARCH Comput. Archit. News 44(4): 38-43 (2016) - [j3]Razvan Nane
, Vlad Mihai Sima
A Survey and Evaluation of FPGA High-Level Synthesis Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1591-1604 (2016) - [c20]Ernst Joachim Houtgast, Vlad Mihai Sima
GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing. ARCS 2016: 130-142 - [c19]Ernst Joachim Houtgast, Vlad Mihai Sima
Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms. FCCM 2016: 28 - [c18]Ernst Joachim Houtgast, Vlad Mihai Sima, Giacomo Marchiori, Koen Bertels, Zaid Al-Ars:
Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms. ReConFig 2016: 1-8 - 2015
- [c17]Shanshan Ren, Vlad Mihai Sima
FPGA acceleration of the pair-HMMs forward algorithm for DNA sequence analysis. BIBM 2015: 1465-1470 - [c16]Nauman Ahmed, Vlad Mihai Sima
Heterogeneous Hardware/Software Acceleration of the BWA-MEM DNA Alignment Algorithm. ICCAD 2015: 240-246 - [c15]Ernst Joachim Houtgast, Vlad Mihai Sima
An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm. SAMOS 2015: 221-227 - 2014
- [c14]Giovanni Mariani, Gianluca Palermo
DRuiD: Designing reconfigurable architectures with decision-making support. ASP-DAC 2014: 213-218 - [c13]Razvan Nane
High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain. EUC 2014: 138-145 - [c12]Mark de Jong, Vlad Mihai Sima
FPGA-accelerated Monte-Carlo integration using stratified sampling and Brownian bridges. FPT 2014: 68-75 - 2013
- [j2]Roel Meeuws, Sayyed Arash Ostadzadeh
Quipu: A Statistical Model for Predicting Hardware Resources. ACM Trans. Reconfigurable Technol. Syst. 6(1): 3:1-3:25 (2013) - [c11]Giovanni Mariani, Vlad Mihai Sima
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction. FPL 2013: 1-8 - 2012
- [b1]Vlad Mihai Sima:
Compiler Assisted Runtime Adaptation. Delft University of Technology, Netherlands, 2012 - [c10]Giovanni Mariani, Vlad Mihai Sima, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano, Koen Bertels:
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures. DATE 2012: 1379-1384 - [c9]Razvan Nane
DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler. FPL 2012: 619-622 - [c8]Razvan Nane
Area constraint propagation in high level synthesis. FPT 2012: 247-252 - [c7]Razvan Nane
A lightweight speculative and predicative scheme for hardware execution. ReConFig 2012: 1-6 - 2011
- [c6]Razvan Nane
IP-XACT extensions for Reconfigurable Computing. ASAP 2011: 215-218 - 2010
- [j1]Koen Bertels, Vlad Mihai Sima
HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms. IEEE Micro 30(5): 88-97 (2010)
2000 – 2009
- 2009
- [c5]Mojtaba Sabeghi, Vlad Mihai Sima
Compiler assisted runtime task scheduling on a reconfigurable computer. FPL 2009: 44-50 - [c4]Vlad Mihai Sima
Runtime decision of hardware or software execution on a heterogeneous reconfigurable platform. IPDPS 2009: 1-6 - [c3]Vlad Mihai Sima
Runtime Memory Allocation in a Heterogeneous Reconfigurable Platform. ReConFig 2009: 71-76 - 2008
- [c2]Vlad Mihai Sima
Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform. FPL 2008: 651-654 - 2007
- [c1]Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte, Georgi Gaydadjiev
HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation. FPL 2007: 402-408
Coauthor Index
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