Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
Authors: 
Simranjeet Singh, Elmira Moussavi, Christopher Bengel, Sachin Patkar, Rainer Waser, Rainer Leupers, Vikas Rana, Vivek Pachauri, Stephan Menzel, Farhad MerchantAuthors Info & Claims
Article No.: 30, Pages 1 - 7
Abstract
Multi-valued logic (MVL), characterized by more than two possible logic states, presents distinct advantages compared to conventional Boolean logic. Novel post-CMOS technologies, particularly memristive and bio-sensitive devices, exhibit compelling attributes that make them promising candidates for realizing MVL computing components. To assess the viability of these devices, we delve into key aspects of Memristive and ISFETs, including their state transition dynamics, multi-level functionality, and compatibility with CMOS manufacturing processes. Through this investigation, we successfully demonstrate the practical implementation of ternary arithmetic MVL gates utilizing memristive and bio-sensitive devices. Our findings affirm that these innovative devices hold the potential to serve as MVL computing elements effectively.
References
[1]
P Bargveld. 2003. Thirty years of ISFETOLOGY - What happened in the past 30 years and what may happen in the next 30 years. Sensors and actuators. B: Chemical 88, 1 (2003), 1–20. https://doi.org/10.1016/S0925-4005(02)00301-5
[2]
Piet Bergveld. 1972. Development, operation, and application of the ion-sensitive field-effect transistor as a tool for electrophysiology. IEEE Transactions on Biomedical Engineering5 (1972), 342–351.
[3]
Elena Dubrova. 1999. Multiple-Valued Logic in VLSI: Challenges and Opportunities. Proceedings of NORCHIP’99 (11 1999).
[4]
Boroumand et al.2018. Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks. ACM SIGPLAN Notices 53 (03 2018), 316–331. https://doi.org/10.1145/3296957.3173177
[5]
Bhattacharjee et al.2018. Multi-valued and Fuzzy Logic Realization using TaOx Memristive Devices. Scientific Reports 8, 8 (2018), 1–10.
[6]
Bengel et al.ISCAS 2021. Implementation of Multinary Lukasiewicz Logic using Memristive Devices. (ISCAS 2021).
[7]
C. Bengel et al.2020. Variability-Aware Modeling of Filamentary Oxide based Bipolar Resistive Switching Cells Using SPICE Level Compact Models. TCAS 1 (2020).
[8]
D. Ielmini et al.2018. In-memory computing with resistive switching devices. Nature Electronics 1, 6 (2018), 333–343.
[9]
Etiemble et al.1988. Comparison of binary and multivalued ICs according to VLSI criteria. Computer 21, 4 (1988), 28–42. https://doi.org/10.1109/2.49
[10]
F. Cueppers et al.2019. Exploiting the switching dynamics of HfO2-based ReRAM devices for reliable analog memristive behavior. APL Mater. 7, 9 (2019), 91105/1–9.
[11]
Hoffer et al.2020. Experimental Demonstration of Memristor-Aided Logic (MAGIC) Using Valence Change Memory (VCM). IEEE Trans. Electron Devices 67, 8 (2020), 3115–3122.
[12]
Ingebrandt et al.2006. Label-free detection of DNA using field-effect transistors. physica status solidi (a) 203, 14 (2006), 3399–3411.
[13]
Keshavarzian et al.2014. A novel CNTFET-based ternary full adder. Circuits, Systems, and Signal Processing 33, 3 (2014), 665–679.
[14]
Lin et al.2009. CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE TNANO 10, 2 (2009), 217–225.
[15]
Miller et al.2007. Multiple valued logic: Concepts and representations. Synthesis lectures on digital circuits and systems 2, 1 (2007), 1–127.
[16]
Nguyen et al.2018. Readout Concepts for Label-Free Biomolecule Detection with Advanced ISFET and Silicon Nanowire Biosensors. (2018).
[17]
Offenh et al.1997. Field-effect transistor array for monitoring electrical activity from mammalian neurons in culture. Biosensors and Bioelectronics 12, 8 (1997), 819–826.
[18]
Pachauri et al.2016. Biologically sensitive field-effect transistors: from ISFETs to NanoFETs. Essays in biochemistry 60, 1 (June 2016), 81—90. https://doi.org/10.1042/ebc20150009
[19]
Raychowdhury et al.2005. Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE TNANO 4, 2 (2005), 168–179.
[20]
Rai et al.DATE 2021. Vertical IP Protection of the Next-Generation Devices: Quo Vadis? (DATE 2021).
[21]
Sprössler et al.1999. Electrical recordings from rat cardiac muscle cells using field-effect transistors. Physical review E 60, 2 (1999), 2171.
[22]
Singh et al.2023. Finite State Automata Design using 1T1R ReRAM Crossbar. In 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS). 1–5. https://doi.org/10.1109/NEWCAS57931.2023.10198206
[23]
S. Kim et al.2012. Selector Devices for Cross-point ReRAM. In 13th CNNA, Turin, ITALY. 2012 13th International Workshop On Cellular Nanoscale Networks and Their Applications (cnna).
[24]
Temel et al.2004. Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits. Analog Integrated Circuits and Signal Processing 39, 2 (2004), 191–204. https://doi.org/10.1023/B:ALOG.0000024066.66847.89
[25]
Wang et al.2021. High-Density Memristor-CMOS Ternary Logic Family. IEEE TCAS I: Regular Papers 68, 1 (2021), 264–274. https://doi.org/10.1109/TCSI.2020.3027693
[26]
W. Kim et al.2016. Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic. Sci. Rep. 6 (2016), 36652.
[27]
Xu et al.2018. Fully Functional Logic-In-Memory Operations Based on a Reconfigurable Finite-State Machine Using a Single Memristor. Advanced Electronic Materials 4 (2018), 1800189.
[28]
Zacherle et al.2016. Resistive switching: from fundamentals of nanoionic redox processes to memristive device applications / Edited by Daniele Ielmini and Rainer Waser. Wiley-VCH, Weinheim. https://doi.org/10.1002/9783527680870.ch3
[29]
Daniel Etiemble. 2003. Why M-valued circuits are restricted to a small niche?Journal of Multiple-Valued Logic and Soft Computing 9 (01 2003), 109–123.
[30]
Daniel Etiemble. 2019. Evolution of Technologies and Multivalued Circuits. CoRR abs/1907.01451 (2019). arxiv:1907.01451http://arxiv.org/abs/1907.01451
[31]
J. W. McPherson. 2007. Reliability Trends with Advanced CMOS Scaling and The Implications for Design. In 2007 IEEE CICC. 405–412. https://doi.org/10.1109/CICC.2007.4405763
[32]
Smith. 1981. The Prospects for Multivalued Logic: A Technology and Applications View. IEEE TC C-30, 9 (1981), 619–634. https://doi.org/10.1109/TC.1981.1675860
[33]
Özer et al.2006. Multiple-valued logic buses for reducing bus energy in low-power systems. Computers and Digital Techniques, IEE Proceedings - 153 (08 2006), 270 – 282. https://doi.org/10.1049/ip-cdt:20050160
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Published In
December 2023
222 pages
ISBN:9798400703256
DOI:10.1145/3611315
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Published: 25 January 2024
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- NEUROTEC
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NANOARCH '23
NANOARCH '23: 18th ACM International Symposium on Nanoscale Architectures
December 18 - 20, 2023
Dresden, Germany
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Overall Acceptance Rate 55 of 87 submissions, 63%
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