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How to Shrink My FPGAs — Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics

Authors:

King Lok Chung,

Dirk KochAuthors Info & Claims

FPGA '22: Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Pages 13 - 23

https://doi.org/10.1145/3490422.3502371

Published: 11 February 2022 Publication History

Abstract

Commercial FPGAs from major vendors are extensively optimized, and fabrics use many hand-crafted custom cells, including switch matrix multiplexers and configuration memory cells. The physical design optimizations commonly improve area, latency (=speed), and power consumption together. This paper is dedicated to improving the physical implementation of FPGA tiles and the configuration storage in SRAM FPGAs. This paper proposes to remap configuration bits and interface wires to implement tightly packed tiles. Using the FABulous FPGA framework, we show that our optimizations are virtually for free but can save over 20% in area and improve latency at the same time. We will evaluate our approach in different scenarios by changing the available metal layers or the requested channel capacity. Our optimizations consider all tiles and we propose a flow that resolves dependencies between the CLBs and other tiles. Moreover, we will show that frame-based reconfiguration is, in almost all cases, better than shift register configuration.

Supplementary Material

MP4 File (FPGA22-fp224.mp4)

This presentation is dedicated to improving the physical implementation of FPGA tiles and the configuration storage in SRAM FPGAs. We remap configuration bits and interface wires to implement tightly packed tiles. By using the FABulous FPGA framework, we show that our optimizations are virtually for free but can save over 20% in area and improve latency at the same time. We explore different scenarios by changing the available metal layers or the requested channel capacity. Our optimizations consider all tiles and we propose a flow that resolves dependencies between the CLBs and other tiles. With this, FABulous FPGAs are currently delivering the best area density by any open-hardware FPGA project.

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Cited By

Johnson JBoxer BPrakash TGrace CSorensen PTripathi M(2024)Investigating resource-efficient neutron/gamma classification ML models targeting eFPGAsJournal of Instrumentation10.1088/1748-0221/19/07/P0703419:07(P07034)Online publication date: 29-Jul-2024
https://doi.org/10.1088/1748-0221/19/07/P07034
Shah MTernes JKoch D(2023)FABulous Demo: Open Source FPGA on Sky1302023 33rd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL60245.2023.00070(365-365)Online publication date: 4-Sep-2023
https://doi.org/10.1109/FPL60245.2023.00070

Index Terms

How to Shrink My FPGAs — Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics
1. Hardware

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cover image ACM Conferences

FPGA '22: Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 2022

211 pages

ISBN:9781450391498

DOI:10.1145/3490422

General Chair:
Michael Adler
Intel, USA
,
Program Chair:
Paolo Ienne
EPFL, Switzerland

Copyright © 2022 ACM.

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Published: 11 February 2022

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FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 27 - March 1, 2022

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Cited By

Johnson JBoxer BPrakash TGrace CSorensen PTripathi M(2024)Investigating resource-efficient neutron/gamma classification ML models targeting eFPGAsJournal of Instrumentation10.1088/1748-0221/19/07/P0703419:07(P07034)Online publication date: 29-Jul-2024
https://doi.org/10.1088/1748-0221/19/07/P07034
Shah MTernes JKoch D(2023)FABulous Demo: Open Source FPGA on Sky1302023 33rd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL60245.2023.00070(365-365)Online publication date: 4-Sep-2023
https://doi.org/10.1109/FPL60245.2023.00070

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