research-article

Design Tools for Implementing Self-Aware and Fault-Tolerant Systems on FPGAs

Authors:

Christian Beckhoff,

Jim TorresenAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 7, Issue 2

Article No.: 14, Pages 1 - 23

https://doi.org/10.1145/2617597

Published: 04 July 2014 Publication History

Abstract

To fully exploit the capabilities of runtime reconfigurable FPGAs in self-aware systems, design tools are required that exceed the capabilities of present vendor design tools. Such tools must allow the implementation of scalable reconfigurable systems with various different partial modules that might be loaded to different positions of the device at runtime. This comprises several complex tasks, including floorplanning, communication architecture synthesis, physical constraints generation, physical implementation, and timing verification all the way down to the final bitstream generation. In this article, we present how our GoAhead framework helps in implementing self-aware systems on FPGAs with a minimum of user interaction.

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Cited By

Rizzi TBaroni AGlukhov ABertozzi DWenger CIelmini DZambelli C(2023)Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAsIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2023.325901523:3(328-336)Online publication date: Sep-2023
https://doi.org/10.1109/TDMR.2023.3259015
Ochoa-Ruiz GWattebled PTouiza MDe Lamotte FBourennane EMeftali SDekeyser JDiguet J(2019)A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-ChipJournal of Parallel and Distributed Computing10.1016/j.jpdc.2017.09.011112:P1(1-19)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.1016/j.jpdc.2017.09.011
Zambelli CCastellari MOlivo PBertozzi D(2018)Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs2018 New Generation of CAS (NGCAS)10.1109/NGCAS.2018.8572050(21-24)Online publication date: Nov-2018
https://doi.org/10.1109/NGCAS.2018.8572050
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Index Terms

Design Tools for Implementing Self-Aware and Fault-Tolerant Systems on FPGAs
1. Computer systems organization

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cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 7, Issue 2

June 2014

199 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/2638850

Issue’s Table of Contents

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 04 July 2014

Accepted: 01 March 2014

Revised: 01 June 2013

Received: 01 January 2013

Published in TRETS Volume 7, Issue 2

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Cited By

Rizzi TBaroni AGlukhov ABertozzi DWenger CIelmini DZambelli C(2023)Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAsIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2023.325901523:3(328-336)Online publication date: Sep-2023
https://doi.org/10.1109/TDMR.2023.3259015
Ochoa-Ruiz GWattebled PTouiza MDe Lamotte FBourennane EMeftali SDekeyser JDiguet J(2019)A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-ChipJournal of Parallel and Distributed Computing10.1016/j.jpdc.2017.09.011112:P1(1-19)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.1016/j.jpdc.2017.09.011
Zambelli CCastellari MOlivo PBertozzi D(2018)Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs2018 New Generation of CAS (NGCAS)10.1109/NGCAS.2018.8572050(21-24)Online publication date: Nov-2018
https://doi.org/10.1109/NGCAS.2018.8572050
Pham KHorta EKoch DVaishnav AKuhn T(2018)IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)10.1109/MCSoC2018.2018.00018(36-43)Online publication date: Sep-2018
https://doi.org/10.1109/MCSoC2018.2018.00018
Ochoa-Ruiz GAguilar-Lobo LBevan Rde Lamotte FDiguet J(2018)Towards Dynamically Reconfigurable SoCs (DRSoCs) in industrial automation: State of the art, challenges and opportunitiesMicroprocessors and Microsystems10.1016/j.micpro.2018.07.00262(20-40)Online publication date: Oct-2018
https://doi.org/10.1016/j.micpro.2018.07.002
Ochoa-Ruiz GGuillet SLamotte FRutten EBourennane EDiguet JGogniat G(2015)An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable SystemsACM Transactions on Design Automation of Electronic Systems10.1145/280078421:1(1-25)Online publication date: 2-Dec-2015
https://dl.acm.org/doi/10.1145/2800784
Beckhoff CKoch DTorresen J(2014)Portable module relocation and bitstream compression for Xilinx FPGAs2014 24th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2014.6927480(1-8)Online publication date: Sep-2014
https://doi.org/10.1109/FPL.2014.6927480

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