default search action
Dimin Niu
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
- [c41]Ruoxi Zhu, Shusong Xu, Peiye Liu, Sicheng Li, Yanheng Lu, Dimin Niu, Zihao Liu, Zihao Meng, Zhiyong Li, Xinhua Chen, Yibo Fan:
Zero-Shot Structure-Preserving Diffusion Model for High Dynamic Range Tone Mapping. CVPR 2024: 26130-26139 - [c40]Teng Ma, Zheng Liu, Chengkun Wei, Jialiang Huang, Youwei Zhuo, Haoyu Li, Ning Zhang, Yijin Guan, Dimin Niu, Mingxing Zhang, Tao Ma:
HydraRPC: RPC in the CXL Era. USENIX ATC 2024: 387-395 - 2023
- [j13]Xinfeng Xie
, Peng Gu
MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing. ACM Trans. Archit. Code Optim. 20(3): 40:1-40:26 (2023) - [j12]Zhenhua Zhu, Hanbo Sun, Tongxin Xie, Yu Zhu, Guohao Dai
MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4112-4125 (2023) - [j11]Yanhong Wang
Accelerating Distributed GNN Training by Codes. IEEE Trans. Parallel Distributed Syst. 34(9): 2598-2614 (2023) - [c39]Zhiyao Li, Jiaxiang Li, Taijie Chen, Dimin Niu, Hongzhong Zheng, Yuan Xie, Mingyu Gao:
Spada: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow. ASPLOS (2) 2023: 747-761 - [c38]Cong Li, Zhe Zhou, Xingchen Li, Guangyu Sun, Dimin Niu:
NMExplorer: An Efficient Exploration Framework for DIMM-based Near-Memory Tensor Reduction. DAC 2023: 1-6 - [c37]Xuanle Ren, Zhaohui Chen, Zhen Gu, Yanheng Lu, Ruiguang Zhong, Wen-Jie Lu, Jiansong Zhang, Yichi Zhang
CHAM: A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product. DAC 2023: 1-6 - [c36]Zheng Qu
TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization. MICRO 2023: 452-464 - 2022
- [j10]Linyong Huang
Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network. IEEE Access 10: 46796-46807 (2022) - [j9]Zhaoyang Du
Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging. IEEE Access 10: 79237-79248 (2022) - [j8]Zhaoyang Du
OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. IEEE Access 10: 85960-85974 (2022) - [j7]Xingchen Li
Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4758-4770 (2022) - [c35]Xingchen Li, Bingzhe Wu
Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network. HPCA 2022: 1043-1055 - [c34]Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie:
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. ICPADS 2022: 483-490 - [c33]Shuangchen Li, Dimin Niu, Yuhao Wang, Wei Han, Zhe Zhang, Tianchan Guan, Yijin Guan, Heng Liu, Linyong Huang, Zhaoyang Du
Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network. ISCA 2022: 946-961 - [c32]Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie:
184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. ISSCC 2022: 1-3 - [c31]Haozhe Zhu
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. ISSCC 2022: 1-3 - [i4]Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie:
Accelerating CPU-based Sparse General Matrix Multiplication with Binary Row Merging. CoRR abs/2206.06611 (2022) - [i3]Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie:
OpSparse: a Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. CoRR abs/2206.07244 (2022) - [i2]Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie:
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. CoRR abs/2207.13848 (2022) - 2021
- [j6]Feng Wang, Guojie Luo, Guang-Yu Sun, Yuhao Wang, Dimin Niu, Hongzhong Zheng:
Area Efficient Pattern Representation of Binary Neural Networks on RRAM. J. Comput. Sci. Technol. 36(5): 1155-1166 (2021) - [j5]Feng Wang
STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 864-877 (2021) - [j4]Peng Gu
DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1586-1599 (2021) - [i1]Xinfeng Xie, Peng Gu, Yufei Ding, Dimin Niu, Hongzhong Zheng, Yuan Xie:
MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing. CoRR abs/2103.06653 (2021) - 2020
- [c30]Zhao Wang, Yijin Guan, Guangyu Sun, Dimin Niu, Yuhao Wang, Hongzhong Zheng, Yinhe Han:
GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks. ACA 2020: 73-86 - [c29]Zhenhua Zhu, Hanbo Sun, Kaizhong Qiu, Lixue Xia, Gokul Krishnan, Guohao Dai, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems. ACM Great Lakes Symposium on VLSI 2020: 83-88 - [c28]Peng Gu
iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture. ISCA 2020: 804-817
2010 – 2019
- 2019
- [c27]Youwei Zhuo, Chao Wang, Mingxing Zhang, Rui Wang, Dimin Niu, Yanzhi Wang, Xuehai Qian:
GraphQ: Scalable PIM-Based Graph Processing. MICRO 2019: 712-725 - 2018
- [c26]Mu-Tien Chang, I. Stephen Choi, Dimin Niu, Hongzhong Zheng:
Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach. ACM Great Lakes Symposium on VLSI 2018: 439-442 - [c25]Shuangchen Li, Alvin Oliver Glova, Xing Hu, Peng Gu, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie:
SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator. MICRO 2018: 696-709 - 2017
- [j3]Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis:
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric. IEEE Micro 37(3): 70-78 (2017) - [c24]Shuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie:
DRISA: a DRAM-based reconfigurable in-situ accelerator. MICRO 2017: 288-301 - [c23]Krishna T. Malladi, Mu-Tien Chang, Dimin Niu, Hongzhong Zheng:
FlashStorageSim: Performance Modeling for SSD Architectures. NAS 2017: 1-2 - 2016
- [c22]Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis:
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric. ISCA 2016: 506-518 - 2015
- [j2]Cong Xu, Yang Zheng, Dimin Niu, Xiaochun Zhu, Seung-Hyuk Kang, Yuan Xie:
Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach. IEEE Trans. Multi Scale Comput. Syst. 1(4): 195-206 (2015) - [j1]Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu
Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design. ACM Trans. Design Autom. Electr. Syst. 20(4): 63:1-63:21 (2015) - [c21]Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu
Overcoming the challenges of crossbar resistive memory architectures. HPCA 2015: 476-488 - 2014
- [c20]Qiaosha Zou, Dimin Niu, Yan Cao, Yuan Xie:
3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code. ASP-DAC 2014: 762-767 - [c19]Cong Xu, Dimin Niu, Shimeng Yu
Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture. ASP-DAC 2014: 825-830 - [c18]Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu
Reliability-aware cross-point resistive memory design. ACM Great Lakes Symposium on VLSI 2014: 145-150 - [c17]Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu
Architecting 3D vertical resistive memory for next-generation storage systems. ICCAD 2014: 55-62 - [c16]Chao Zhang, Guangyu Sun, Peng Li
SBAC: a statistics based cache bypassing method for asymmetric-access caches. ISLPED 2014: 345-350 - 2013
- [c15]Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Understanding the trade-offs in multi-level cell ReRAM memory design. DAC 2013: 108:1-108:6 - [c14]Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. ICCAD 2013: 17-23 - [c13]Dimin Niu, Qiaosha Zou, Cong Xu, Yuan Xie:
Low power multi-level-cell resistive memory design with incomplete data mapping. ICCD 2013: 131-137 - 2012
- [c12]Dimin Niu, Yang Xiao, Yuan Xie:
Low power memristor-based ReRAM design with Error Correcting Code. ASP-DAC 2012: 79-84 - [c11]Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Design trade-offs for high density cross-point resistive memory. ISLPED 2012: 209-214 - [r1]Yiran Chen, Hai Li, Yuan Xie, Dimin Niu:
Low-Power Design of Emerging Memory Technologies. Handbook of Energy-Aware and Green Computing 2012: 67-90 - 2011
- [c10]Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie:
A frequent-value based PRAM memory architecture. ASP-DAC 2011: 211-216 - [c9]Cong Xu, Dimin Niu, Xiaochun Zhu, Seung-Hyuk Kang, Matt Nowak, Yuan Xie:
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems. ICCAD 2011: 463-470 - [c8]Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie:
Energy-efficient multi-level cell phase-change memory system with data encoding. ICCD 2011: 175-182 - [c7]Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu:
F2BFLY: an on-chip free-space optical network with wavelength-switching. ICS 2011: 348-358 - 2010
- [c6]Dimin Niu
Energy and performance driven circuit design for emerging phase-change memory. ASP-DAC 2010: 193-198 - [c5]Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie:
Impact of process variations on emerging memristor. DAC 2010: 877-882 - [c4]Yongsoo Joo, Dimin Niu
Energy- and endurance-aware design of phase change memory caches. DATE 2010: 136-141 - [c3]Guangyu Sun, Yongsoo Joo
A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. HPCA 2010: 1-12 - [c2]Yibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis. ICCAD 2010: 471-476 - [c1]Dimin Niu, Yiran Chen, Yuan Xie:
Low-power dual-element memristor based memory design. ISLPED 2010: 25-30
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-08 20:35 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: