research-article

Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach

Authors:

Mu-Tien Chang,

I. Stephen Choi,

Dimin Niu,

Hongzhong ZhengAuthors Info & Claims

GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI

Pages 439 - 442

https://doi.org/10.1145/3194554.3194633

Published: 30 May 2018 Publication History

Get Access

Abstract

This paper presents a performance analysis framework for studying emerging memories. The key component of the framework is a memory-latency programmable emulator, which is based on a FPGA-attached server system. The emulator allows users extend read and/or write latency. In addition, we use regression models to enable system performance studies for memory latencies beyond hardware limitations. Finally, we demonstrate Spark application case studies, analyzing the impact of two key characteristics of emerging memories: extended memory access times and enlarged memory capacities. Results show that the benefit of high capacity memory could outweigh the performance loss due to longer memory latency.

References

[1]

Apache Spark. spark.apache.org.

Google Scholar

[2]

An Introduction to the Intel QuickPath Interconnect. Intel, 2009.

Google Scholar

[3]

Mllib | apache spark, 2015.

Google Scholar

[4]

N. Binkert et al. The Gem5 Simulator. SIGARCH Computer Architecture News, 39(2):1--7, Aug. 2011.

Digital Library

Google Scholar

[5]

I. S. Choi et al. Early Experience with Optimizing I/O Performance Using High-Performance SSDs for In-Memory Cluster Computing. In BigData, 2015.

Digital Library

Google Scholar

[6]

R. Clapp et al. Quantifying the Performance Impact of Memory Latency and Bandwidth for Big Data Workloads. In IISWC, 2015.

Digital Library

Google Scholar

[7]

P. Gupta. Xeon+ FPGA Platform for the Data Center. CARL, 2015.

Google Scholar

[8]

B. Lee et al. Architecting Phase Change Memory As a Scalable DRAM Alternative. In ISCA, 2009.

Digital Library

Google Scholar

[9]

K. Malladi et al. FAME: A Fast and Accurate Memory Emulator for New Memory System Architecture Exploration. In MASCOTS, 2015.

Digital Library

Google Scholar

[10]

A. Patel, F. Afram, S. Chen, and K. Ghose. Marss: A full system simulator for multicore x86 cpus. In DAC, pages 1050--1055, 2011.

Digital Library

Google Scholar

[11]

P. Rosenfeld et al. DRAMSim2: A Cycle Accurate Memory System Simulator. IEEE CAL, 10(1):16--19, Jan. 2011.

Digital Library

Google Scholar

[12]

J. Stevens et al. An Integrated Simulation Infrastructure for the Entire Memory Hierarchy: Cache, DRAM, Nonvolatile Memory, and Disk. Intel Technology Journal, 17(1):184--200, 2013.

Google Scholar

[13]

L. Wang et al. BigDataBench: A Big Data Benchmark Suite from Internet Services. In HPCA, 2014.

Crossref

Google Scholar

[14]

C. Xu et al. Overcoming the Challenges of Crossbar Resistive Memory Architectures. In HPCA, 2015.

Crossref

Google Scholar

Cited By

View all

Soriano TNovo DPrenat GPendina GBenoit P(2022)MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC54400.2022.9939630(1-6)Online publication date: 3-Oct-2022
https://doi.org/10.1109/VLSI-SoC54400.2022.9939630
Kolajo TDaramola OAdebiyi A(2019)Big data stream analysis: a systematic literature reviewJournal of Big Data10.1186/s40537-019-0210-76:1Online publication date: 6-Jun-2019
https://doi.org/10.1186/s40537-019-0210-7

Index Terms

Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach
1. Hardware
  1. Emerging technologies
    1. Analysis and design of emerging devices and systems

Recommendations

Embedded memory technologies: Present and future

This issue of D&T features seven articles on the future landscape of embedded memories. The articles address emerging memories and the unique challenges of nanoscale memory technologies.
Modeling, Architecture, and Applications for Emerging Memory Technologies

Editor's note:Spin-transfer torque RAM and phase-change RAM are vying to become the next-generation embedded memory, offering high speed, high density, and nonvolatility. This article discusses new opportunities and challenges presented by these two ...
A secure and authenticated host-to-memory communication interface
CF '19: Proceedings of the 16th ACM International Conference on Computing Frontiers

Emerging non-volatile memories (NVMs) have the potential to change the memory-storage hierarchy in computing devices, and even to replace DRAM as main memories. In fact NVMs, beside offering byte-addressability and data persistence, promise better ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI

May 2018

533 pages

ISBN:9781450357241

DOI:10.1145/3194554

General Chair:
Deming Chen
University of Illinois, USA
,
Program Chairs:
Houman Homayoun
George Mason University, USA
,
Baris Taskin
Drexel University, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 May 2018

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

GLSVLSI '18

Sponsor:

SIGDA

GLSVLSI '18: Great Lakes Symposium on VLSI 2018

May 23 - 25, 2018

IL, Chicago, USA

Acceptance Rates

GLSVLSI '18 Paper Acceptance Rate 48 of 197 submissions, 24%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
137
Total Downloads

Downloads (Last 12 months)5
Downloads (Last 6 weeks)0

Reflects downloads up to 14 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Soriano TNovo DPrenat GPendina GBenoit P(2022)MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC54400.2022.9939630(1-6)Online publication date: 3-Oct-2022
https://doi.org/10.1109/VLSI-SoC54400.2022.9939630
Kolajo TDaramola OAdebiyi A(2019)Big data stream analysis: a systematic literature reviewJournal of Big Data10.1186/s40537-019-0210-76:1Online publication date: 6-Jun-2019
https://doi.org/10.1186/s40537-019-0210-7

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Embedded memory technologies: Present and future

Modeling, Architecture, and Applications for Emerging Memory Technologies

A secure and authenticated host-to-memory communication interface