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MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems

Published: 07 September 2020 Publication History

Abstract

Memristor based neuromorphic computing systems give alternative solutions to boost the computing energy efficiency of Neural Network (NN) algorithms. Because of the large-scale applications and the large architecture design space, many factors will affect the computing accuracy and system's performance. In this work, we propose a behavior-level modeling tool for memristor-based neuromorphic computing systems, MNSIM 2.0, to model the performance and help researchers to realize an early-stage design space exploration. Compared with the former version and other benchmarks, MNSIM 2.0 has the following new features: 1. In the algorithm level, MNSIM 2.0 supports the inference accuracy simulation for mixed-precision NNs considering non-ideal factors. 2. In the architecture level, a hierarchical modeling structure for PIM systems is proposed. Users can customize their designs from the aspects of devices, interfaces, processing units, buffer designs, and interconnections. 3. Two hardware-aware algorithm optimization methods are integrated in MNSIM 2.0 to realize software-hardware co-optimization.

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References

[1]
H. Chen et al. 2018. A >3GHz ERBW 1.1GS/s 8b Two-Sten SAR ADC with Recursive-Weight DAC. In VLSI-Circuits, 2018. 97--98.
[2]
P.Chietal.2016.PRIME:ANovelProcessing-in-memoryArchitectureforNeural Network Computation in ReRAM-based Main Memory. In ISCA, 2016.
[3]
K. D. Choo, J. Bell, and M. P. Flynn. 2016. 27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC. In ISSCC, 2016. 460--461.
[4]
X. Dong et al. 2012. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. IEEE TCAD (2012).
[5]
K. He et al. 2016. Deep Residual Learning for Image Recognition. In CVPR, 2016.
[6]
Z. He et al. 2019. Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping. In DAC, 2019. 1--6.
[7]
Kaggle et al. 2014. CIFAR-10 - Object Recognition in Images. website. (2014). https://www.kaggle.com/c/cifar-10.
[8]
S. Karen et al. 2014. Very Deep Convolutional Networks for Large-Scale Image Recognition. Computer Science (2014).
[9]
G. Krishnan et al. 2020. Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs. IEEE Design and Test (2020), 1--1.
[10]
L. Kull et al. 2017. 28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. In ISSCC, 2017. 474--475.
[11]
Y. LeCun et al. 1998. Gradient-based learning applied to document recognition. In Proceedings of the IEEE, 1998. 2278--2324.
[12]
M.Lin et al. 2018. DL-RSIM: A Simulation Framework to Enable Reliable ReRAM-based Accelerators for Deep Learning. In ICCAD, 2018. 1--8.
[13]
Sumit K. Mandal et al. 2019. Analytical Performance Models for NoCs with Multiple Priority Traffic Classes. ACM Trans. Embed. Comput. Syst. 18, 5s, Article 52 (Oct. 2019), 21 pages.
[14]
B. Nasri et al.2017. A700 ""W 1GS/s 4-bit folding-flash ADC in 65nm CMOS for wide band wireless communications. In ISCAS, 2017. 1--4.
[15]
X. Peng et al. 2019. DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies. In IEDM, 2019. 32.5.1--32.5.4.
[16]
A. Shafiee et al. 2016. ISAAC: A Convolutional Neural Network Accelerator with In-situ Analog Arithmetic in Crossbars. In ISCA, 2016.
[17]
H. Sun et al. 2020. An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators. In ASPDAC, 2020. 1--6.
[18]
S. J. E. Wilton and N. P. Jouppi. 1996. CACTI: an enhanced cache access and cycle time model. JSSC, 1996 31, 5 (1996), 677--688.
[19]
W. Wu et al. 2018. Suppress variations of analog resistive memory for neuromorphic computing by localizing Vo formation, In ISCAS, 2017. Journal of Applied Physics 124, 15.
[20]
L. Xia et al. 2018. MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. TCAD, 2018 (2018).
[21]
W. Zhang et al. 2019. Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis. In DAC, 2019. 1--6.
[22]
Z. Zhu et al. 2019. A Configurable Multi-Precision CNN Computing Framework Based on Single Bit RRAM. In DAC, 2019. 1--6.

Cited By

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  • (2025)Approximation-Aware Training for Efficient Neural Network Inference on MRAM Based CiM ArchitectureIEEE Open Journal of Nanotechnology10.1109/OJNANO.2024.35242656(16-26)Online publication date: 2025
  • (2025)Layer ensemble averaging for fault tolerance in memristive neural networksNature Communications10.1038/s41467-025-56319-616:1Online publication date: 1-Feb-2025
  • (2024)PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546788(1-2)Online publication date: 25-Mar-2024
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cover image ACM Other conferences
GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI
September 2020
597 pages
ISBN:9781450379441
DOI:10.1145/3386263
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 September 2020

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Author Tags

  1. hardware modeling
  2. memristor
  3. processing-in-memory

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  • Research-article

Funding Sources

  • National Natural Science Foundation of China
  • Beijing Academy of Artificial Intelligence under Grant
  • National Key Research and Development Program of China
  • Beijing National Research Center for Information Science and Technology
  • Beijing Innovation Center for Future Chips

Conference

GLSVLSI '20
GLSVLSI '20: Great Lakes Symposium on VLSI 2020
September 7 - 9, 2020
Virtual Event, China

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2025)Approximation-Aware Training for Efficient Neural Network Inference on MRAM Based CiM ArchitectureIEEE Open Journal of Nanotechnology10.1109/OJNANO.2024.35242656(16-26)Online publication date: 2025
  • (2025)Layer ensemble averaging for fault tolerance in memristive neural networksNature Communications10.1038/s41467-025-56319-616:1Online publication date: 1-Feb-2025
  • (2024)PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546788(1-2)Online publication date: 25-Mar-2024
  • (2024)ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546504(1-2)Online publication date: 25-Mar-2024
  • (2024)Real-time Blood Pressure Prediction on Wearables with Edge-Based DNNs: A Co-Design ApproachACM Transactions on Design Automation of Electronic Systems10.1145/369951230:1(1-24)Online publication date: 7-Oct-2024
  • (2024)AUTOHET: An Automated Heterogeneous ReRAM-Based Accelerator for DNN InferenceProceedings of the 53rd International Conference on Parallel Processing10.1145/3673038.3673143(1052-1061)Online publication date: 12-Aug-2024
  • (2024)NavCim: Comprehensive Design Space Exploration for Analog Computing-in-Memory ArchitecturesProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676946(168-182)Online publication date: 14-Oct-2024
  • (2024)EPIM: Efficient Processing-In-Memory Accelerators based on EpitomeProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3657377(1-6)Online publication date: 23-Jun-2024
  • (2024)Enhancing ConvNets With ConvFIFO: A Crossbar PIM Architecture Based on Kernel-Stationary First-In-First-Out DataflowIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.340964832:9(1640-1651)Online publication date: Sep-2024
  • (2024)Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-Based DNN AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.340919343:12(4558-4571)Online publication date: Dec-2024
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