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10th VLSI Design 1997: Hyderabad, India
- 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India. IEEE Computer Society 1997, ISBN 0-8186-7755-4
Tutorials
- K. R. Rao, Magdy A. Bayoumi, T. V. Subramaniam:
T1: Multimedia. 2 - P. A. Subrahmanyam, R. Gupta, B. S. Rao:
T2: HW-SW Codesign. 2 - Dinesh P. Mehta
, Naveed A. Sherwani, A. Bariya:
T3: Physical Design. 3 - Rajesh Raina, Jacob A. Abraham, A. K. Pujari:
T4: Verification. 3 - Kaushik Roy, Rabindra K. Roy, Ramesh Harjani, K. S. Murthy:
T5: Low-Power Design. 4 - P. Meyer:
T6: C++/java(Tm)/unix. 4
Session 1: Monday Keynote Address
- Kamran Eshraghian:
Opto-VLSI Systems for Multimedia Computing. 6-9
Session 2: Physical Design
- Pinaki Mazumdar:
Parallel VLSI-Routing Models for Polymorphic Processors Array. 10-14 - Avaneendra Gupta, John P. Hayes:
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. 15-20 - Jianzhong Shi, Akash Randhar, Dinesh Bhatia:
Macro Block Based FPGA Floorplanning. 21-26 - Jens Lienig:
Channel and Switchbox Routing with Minimized Crosstalk - A Parallel Genetic Algorithm Approach. 27-31 - Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan:
A New Partitioning Strategy Based on Supermodular Functions. 32-37 - R. V. Raj, N. S. Murty, P. S. Nagendra Rao, Lalit M. Patnaik:
Effective Heuristics for Timing Driven Constructive Placement. 38-45
Session 3: Synthesis
- Bernd Becker, Rolf Drechsler:
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions. 46-50 - Gary William Grewal, Thomas Charles Wilson:
An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design. 51-56 - Madhav Y. Chikodikar, Shridhar Laddha, Ashish Sirasao:
A Technology Mapper for Xilinx FPGAs. 57-61 - Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar:
Rapid Synthesis of Multi-Chip Systems. 62-68 - Gagan Hasteer, Prithviraj Banerjee:
Simulated Annealing Based Parallel State Assignment of Finite State Machines. 69-75 - Montek Singh, Steven M. Nowick:
Synthesis for Logical Initializability of Synchronous Finite State Machines. 76-81
Session 4: Delay Test and Timing
- Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy:
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. 82-87 - Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal:
Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. 88-94 - Mukund Sivaraman, Andrzej J. Strojwas:
Primitive Path Delay Fault Identification. 95-100 - Bernd Becker, Rolf Drechsler, Sudhakar M. Reddy:
(Quasi-) Linear Path Delay Fault Tests for Adders. 101-105 - Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das:
Delay Fault Coverage Enhancement Using Multiple Test Observation Times. 106-110 - A. Dharchoudhuri, S. M. Kang:
Analytical Fast Timing Simulation of MOS Circuits Driving RC Interconnects. 111-117
Session 5: High-Level Synthesis
- C. P. Ravikumar, R. Aggarwal, C. Sharma:
A Graph-Theoretic Approach for Register File Based Synthesis. 118-123 - Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. 124-129 - Heman Khanna, M. Balakrishnan:
Allocation of FIFO Structures in RTL Data Paths. 130-133 - A. R. Naseer, M. Balakrishnan, Anshul Kumar:
Optimal Clock Period for Synthesized Data Paths. 134-139 - Madhavi Vootukuru, Ranga Vemuri, Nand Kumar:
Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs. 140-145
Session 6: HW-SW Codesign
- Reiner W. Hartenstein, Jürgen Becker:
Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. 146-150 - Santonu Sarkar
Analyzing Controllability of a Hardware Circuit for its Reuse. 151-154 - Debanjan Saha, Anupam Basu, Raj S. Mitra:
Hardware Software Partitioning Using Genetic Algorithm. 155-160 - José M. Mendías, Román Hermida, Milagros Fernández:
Formal Techniques for Hardware Allocation. 161-165 - Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose:
Design Space Exploration for Data Path Synthesis. 166-173
Session 7: Low-Power Design
- Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya:
Algorithms for Low Power FIR Filter Realization Using Differential Coefficients. 174-178 - Priya Patil, Tan-Li Chou, Kaushik Roy, Rabindra Roy:
Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique. 179-184 - Vivek Tiwari, Ryan Donnelly, Sharad Malik
Dynamic Power Management for Microprocessors: A Case Study. 185-192 - Vishwani D. Agrawal:
Low-Power Design by Hazard Filtering. 193-197 - S. Ramanathan, V. Visvanathan:
Low-Power Configurable Processor Array for DLMS Adaptive Filtering. 198-207
Session 8: Parallel Exhibitor Presentations
Session 9: Verification
- Sreeranga P. Rajan, Natarajan Shankar, Mandayam K. Srivas:
Industrial Strength Formal Verification Techniques for Hardware Designs. 208-212 - Gitanjali Swamy:
Formal Verification of Digital Systems. 213-217 - Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli:
Formal Verification of Combinational Circuit. 218-225 - I. Chakrabarti, Dipankar Sarkar, Arun K. Majumdar:
Inductive Verification of Sequential Circuits with a Datapath. 226-231 - Rajeev Murgai, Masahiro Fujita:
Some Recent Advances in Software and Hardware Logic Simulation. 232-238 - S. Harikumer, Shashi Kumar:
Multiobjective Search Based Algorithms for Circuit Partitioning Problem for Acceleration of Logic Simulation. 239-243
Session 10: VLSI Systems
- Sunil Nanda:
Media Processors. 244-246 - Partha Sarathi Bhattacharjee, Sajal K. Das, Debashis Saha, D. Roychowdhury, Parimal Pal Chaudhuri:
A Parallel Architecture for Video Compression. 247-252 - Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili:
Design of a VLSI Hardware PET Decoder. 253-256 - Gab Joong Jeong, Kyoung Hwan Kwon, Moon Key Lee, Seung Han An:
A Scalable Memory System Design. 257-260 - Milind B. Kamble, Kanad Ghose:
Energy-Efficiency of VLSI Caches: A Comparative Study. 261-267 - Preeti Ranjan Panda, Nikil D. Dutt
Behavioral Array Mapping into Multiport Memories Targeting Low Power. 268-273
Session 11: Testability Enhancement
- Richard M. Chou, Kewal K. Saluja:
Sequential Circuit Testing: From DFT to SFT. 274-278 - Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth:
Synthesis for Testability by Two-Clock Control. 279-283 - Sudipta Bhawmik, Indradeep Ghosh:
A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits. 284-288 - Debashis Bhattacharya, Smith Freeman, Bill Lin:
Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit. 289-296 - Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
Efficient Implementation of Multiple On-Chip Signature Checking. 297-302 - Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya:
New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults. 303-309
Session 12: Banquet Keynote
- Walden C. Rhines:
Developing A New Approach For Multimedia Design. 310-313
Session 13: Tuesday Keynote Address
- Tomas W. Williams:
Design For Testability: Today And In The Future. 314-317
Session 14: Asynchronous Design
- Kimberly D. Emerson:
Asynchronous Design - An Interesting Alternative. 318-321 - Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho:
Delay-Insensitive Carry-Lookahead Adders. 322-328 - Radhakrishna Nagalla, Graham R. Hellestrand:
A Visual Approach for Asynchronous Circuit Synthesis. 329-335 - Kamran Eshraghian, Juan A. Montiel-Nelson, Saeid Nooshabadi:
An Asynchronous Morphological Processor for Multi-Media Applications. 336-341 - K. Nanda, S. K. Desai, S. K. Roy:
A New Methodology for the Design of Asynchronous Digital Circuits. 342-347 - Raj S. Mitra, Bishnupriya Bhattacharya, Luciano Lavagno:
Asynchronous Implementation of Synchronous Esterel Specifications. 348-355
Session 15: Diagnosis
- Dinesh Bhatia:
Reconfigurable Computing. 356-359 - Eshwar Belani, Ravi Mittal:
A General Reconfiguration Technique for Fault Tolerant Processor Architectures. 360-363 - Gosta Pada Biswas, Idranil Sen Gupta:
Design of t-UED/AUED Codes from Berger's AUED Code. 364-369 - Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar:
A Novel Reconfigurable Co-Processor Architecture. 370-375 - Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs:
Characterization and Implicit Identification of Sequential Indistinguishability. 376-380 - Srikanth Venkataraman, W. Kent Fuchs:
Distributed Diagnostic Simulation of Stuck-At Faults in Sequential Circuits. 381-387
Session 16: Test and Fault Modeling
- Abhijit Chatterjee, Naveena Nagi:
Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial. 388-392 - Heebyung Yoon, Abhijit Chatterjee, Joseph L. A. Hughes:
Optimal Design of Checksum-Based Checkers for Fault Detection in Linear Analog Circuits. 393-397 - Bapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi:
Pseudoduplication - An ACOB Technique for Single-Ended Circuits. 398-402 - Premal Buch, Ernest S. Kuh:
SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits. 403-407 - Pramodchandran N. Variyam, Abhijit Chatterjee:
FLYER: Fast Fault Simulation of Linear Analog Circuits Using Polynomial Waveform and Perturbed State Representation. 408-412 - Haiming Jin, Ravishankar K. Iyer, Mei-Chen Hsueh:
FAMAS: FAult Modeling via Adaptive Simulation. 413-419
Session 17: Mixed-Signal Design
- D. L. Grundy, M. Bozic, John V. Hatfield:
Development of an Analogue Microprocessor. 420-424 - V. Ravindra Babu, Baquer Mazhari, M. M. Hasan:
An Expert System Approach to Analog Circuit Synthesis. 425-428 - Pradip Mandal, V. Visvanathan:
A Self-Biased High Performance Folded Cascode CMOS Op-Amp. 429-434 - K. Ravi Shankar, K. Radhakrishna Rao, Srinivasan Venkatraman:
Tuning Schemes for Transmission Zeros of Continuous-Time Filters. 435-438 - K. Ravi Shanker, Vinita Vasudevan:
Synthesis of Analog CMOS Circuits. 439-445
Session 18: Architecture
- Ashley Rasquinha, N. Ranganathan:
C3L: A Chip for Connected Component Labeling. 446-450 - Saeid Nooshabadi, Juan A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhuri:
Micropipeline Architecture for Multiplier-less FIR Filters. 451-456 - Palash Sarkar, Bimal K. Roy, Pabitra Pal Choudhury:
VLSI Implementation of Modulo Multiplication Using Carry Free Addition. 457-460 - Tales Cleber Pimenta, Luiz Lenarth Gabriel Vermaas, Paulo César Crepaldi, Robson L. Moreno:
The Design of A Digital IC for Thyristor Triggering. 461-464 - Rana Barua, Samik Sengupta:
Architectures for Arithmetic over GF(2m). 465-469
Session 9: ATPG and Fault Simulation
- Irith Pomeranz, Sudhakar M. Reddy:
On the Detection of Reset Faults in Synchronous Sequential Circuits. 470-474 - Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee:
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. 475-481 - C. P. Ravikumar, Vikas Jain, Anurag Dod:
Faster Fault Simulation Through Distributed Computing. 482-487 - Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler:
Deriving Signal Constraints to Accelerate Sequential Test Generation. 488-494 - Elizabeth M. Rudnick, Janak H. Patel:
Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. 495-503
Session 20: Synthesis and CAD
- Hortensia Mecha, Milagros Fernández:
Interconnection Delay and Clock Cycle Selection in High Level Synthesis. 504-505 - Thomas Charles Wilson, Gary William Grewal:
Shake And Bake: A Method of Mapping Code to Irregular DSPs. 506-508 - Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin:
A Simulation Methodology for Software Energy Evaluation. 509-510 - Rolf Drechsler:
Pseudo Kronecker Expressions for Symmetric Functions. 511-513 - James Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal:
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. 514-515 - Subir Bandyopadhyay, Arunita Jaekel, Graham A. Jullien:
A Method for Synthesizing Area Efficient Multilevel PTL Circuits. 516-519
Session 21: Design and Implementation
- Ron Lin:
Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes. 520-522 - R. Maheshwari, S. S. S. P. Rao, E. G. Poonach:
FPGA Implementation of Median Filter. 523-524 - Subhashish Mukherjee, C. Srinivasan, Vivek Pawar, Sumeet Mathur, Kiran Godbole, Eric Soenen:
A 2.5 V 10 bit SAR ADC. 525-526 - Santanu Chattopadhyay, Parimal Pal Chaudhuri:
Parallel Decoder for Cellular Automata Based Byte Error Correcting Code. 527-528 - Gosta Pada Biswas, Indranil Sengupta:
A Design Technique of TSC Checker for Borden's Code. 529-530 - Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal:
An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing. 531-533
Session 22: Test and DFT
- Irith Pomeranz, Sudhakar M. Reddy:
On Full Reset as a Design-For-Testability Technique. 534-536 - Huy Nguyen, Abhijit Chatterjee, Rabindra K. Roy:
Impact of Partial Reset on Fault Independent Testing and BIST. 537-539 - Raghuram S. Tupuri, Jacob A. Abraham:
A Novel Hierarchical Test Generation Method for Processors. 540-541 - Charles R. Graham, Elizabeth M. Rudnick, Janak H. Patel:
Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits. 542-544 - Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana:
Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using IDDQ Testing in BiCMOS and CMOS Circuits. 545-546 - Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri:
On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. 547-563
Session 23: Panel Discussion: The Future of the Indian Information Technology Industry - A CEO's Roundtable
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