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Vinita Vasudevan
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2020 – today
- 2023
- [j20]Shivani Bathla, Vinita Vasudevan:
IBIA: An Incremental Build-Infer-Approximate Framework for Approximate Inference of Partition Function. Trans. Mach. Learn. Res. 2023 (2023) - [j19]Shivani Bathla
, Vinita Vasudevan
A Framework for Reliability Analysis of Combinational Circuits Using Approximate Bayesian Inference. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 543-554 (2023) - [c17]Shivani Bathla, Vinita Vasudevan:
Approximate inference of marginals using the IBIA framework. NeurIPS 2023 - [i6]Shivani Bathla, Vinita Vasudevan:
IBIA: An Incremental Build-Infer-Approximate Framework for Approximate Inference of Partition Function. CoRR abs/2304.06366 (2023) - [i5]Shivani Bathla, Vinita Vasudevan:
Approximate inference of marginals using the IBIA framework. CoRR abs/2306.00335 (2023) - 2022
- [j18]V. Charumathi
Fast and Accurate Proper Orthogonal Decomposition using Efficient Sampling and Iterative Techniques for Singular Value Decomposition. ACM Trans. Math. Softw. 48(2): 16:1-16:24 (2022) - [i4]Shivani Bathla, Vinita Vasudevan:
IBIA: Bayesian Inference via Incremental Build-Infer-Approximate operations on Clique Trees. CoRR abs/2202.12003 (2022) - [i3]Shivani Bathla, Vinita Vasudevan:
MPE inference using an Incremental Build-Infer-Approximate Paradigm. CoRR abs/2206.01954 (2022) - 2021
- [j17]Celia Dharmaraj
Analysis of power-accuracy trade-off in digital signal processing applications using low-power approximate adders. IET Comput. Digit. Tech. 15(2): 97-111 (2021) - [j16]Basava Naga Girish Koneru
A Smoothed LASSO-Based DNN Sparsification Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4287-4298 (2021) - [j15]Celia Dharmaraj
Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders. ACM Trans. Embed. Comput. Syst. 20(2): 12:1-12:25 (2021)
2010 – 2019
- 2019
- [j14]Basava Naga Girish Koneru
Sparse Artificial Neural Networks Using a Novel Smoothed LASSO Penalization. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 848-852 (2019) - [j13]P. R. Chithira
Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis Framework. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1438-1449 (2019) - [i2]V. Charumathi, M. Ramakrishna, Vinita Vasudevan
Fast Proper Orthogonal Decomposition Using Improved Sampling and Iterative Techniques for Singular Value Decomposition. CoRR abs/1905.05107 (2019) - 2018
- [c16]D. Celia, Vinita Vasudevan
Optimizing power-accuracy trade-off in approximate adders. DATE 2018: 1488-1491 - [c15]D. Celia, Vinita Vasudevan
Probabilistic Error Modeling for Two-part Segmented Approximate Adders. ISCAS 2018: 1-5 - 2017
- [j12]P. R. Chithira, Vinita Vasudevan
A Hierarchical Technique for Statistical Path Selection and Criticality Computation. ACM Trans. Design Autom. Electr. Syst. 23(1): 9:1-9:24 (2017) - [i1]Vinita Vasudevan
A Hierarchical Singular Value Decomposition Algorithm for Low Rank Matrices. CoRR abs/1710.02812 (2017) - 2016
- [j11]Ramprasath S
Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient. ACM Trans. Design Autom. Electr. Syst. 21(4): 66:1-66:27 (2016) - [j10]Ramprasath S
A Skew-Normal Canonical Model for Statistical Static Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2359-2368 (2016) - 2015
- [c14]S. Ramprasath
An efficient algorithm for statistical timing yield optimization. DAC 2015: 166:1-166:6 - [c13]Vinita Vasudevan
An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor form. DAC 2015: 187:1-187:6 - 2014
- [j9]S. Ramprasath
Statistical Criticality Computation Using the Circuit Delay. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5): 717-727 (2014) - 2012
- [c12]S. Ramprasath
On the computation of criticality in statistical timing analysis. ICCAD 2012: 172-179
2000 – 2009
- 2009
- [j8]Vinita Vasudevan
Analysis of Clock Jitter in Continuous-Time Sigma-Delta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(3): 519-528 (2009) - 2006
- [j7]K. N. Vikram, Vinita Vasudevan
Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures. IEEE Trans. Very Large Scale Integr. Syst. 14(9): 1010-1023 (2006) - [c11]K. N. Vikram, Vinita Vasudevan
Scheduling divisible loads on partially reconfigurable hardware. FCCM 2006: 289-290 - 2005
- [j6]K. N. Vikram, Vinita Vasudevan
Hardware-software co-simulation of bus-based reconfigurable systems. Microprocess. Microsystems 29(4): 133-144 (2005) - [j5]Sunil Rafeeque, Vinita Vasudevan
A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(11): 2348-2357 (2005) - [c10]Vinita Vasudevan:
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits. DAC 2005: 397-402 - 2004
- [j4]Sunil Rafeeque, Vinita Vasudevan
A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs. J. Electron. Test. 20(6): 623-638 (2004) - [j3]Vinita Vasudevan
A time-domain technique for computation of noise-spectral density in linear and nonlinear time-varying circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(2): 422-433 (2004) - [j2]Vinita Vasudevan
Computation of the average and harmonic noise power-spectral density in switched-capacitor circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(11): 2165-2174 (2004) - [j1]Vinita Vasudevan
A simple technique to evaluate the noise spectral density in operational amplifier based circuits using the adjoint network theory. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(11): 2175-2178 (2004) - [c9]Sunil Rafeeque, Vinita Vasudevan:
An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC. ISCAS (1) 2004: 281-284 - [c8]Sunil Rafeeque
A Built-in-Self-Test Scheme for Digital to Analog Converters. VLSI Design 2004: 1027- - 2003
- [c7]Vinita Vasudevan, M. Ramakrishna:
Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique. DAC 2003: 538-541 - [c6]Vinita Vasudevan:
A time-domain technique for computation of noise spectral density in switched capacitor circuits. ISCAS (1) 2003: 585-588 - 2000
- [c5]Ranjit K. Dash, T. Pramod, Vinita Vasudevan, M. Ramakrishna:
A Transistor Level Placement Tool for Custom Cell Generation. VLSI Design 2000: 254-257 - [c4]Rajesh T. N. Rajaram, Vinita Vasudevan:
Optimization of the One-Dimensional Full Search Algorithm and Implementation Using an EPLD. VLSI Design 2000: 336-341
1990 – 1999
- 1998
- [c3]C. F. Prince, Vinita Vasudevan:
Symbolic Analysis of Analog Integrated Circuits. VLSI Design 1998: 167- - [c2]Prakash Gopalakrishnan, Vinita Vasudevan:
A Modified Line Expansion Algorithm for Device-level Routing of Analog Circuits. VLSI Design 1998: 249-252 - 1997
- [c1]K. Ravi Shanker, Vinita Vasudevan:
Synthesis of Analog CMOS Circuits. VLSI Design 1997: 439-445
Coauthor Index
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