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Tan-Li Chou
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2020 – today
- 2024
- [c13]Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang
, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. ISSCC 2024: 572-574 - 2023
- [c12]Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang
A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update. ISSCC 2023: 132-133 - [c11]Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Yen-An Chang, Cheng-Han Lu, Yu-Lin Chen, Chieh-Pu Lo, Chung-Chieh Chen, Cheng-Hsiung Kuo, Tan-Li Chou, Chia-Yu Wang, J. J. Wu, Roger Wang, Harry Chuang, Yih Wang
A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity. ISSCC 2023: 494-495 - 2022
- [c10]Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang
A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. ISSCC 2022: 1-3 - [c9]Chia-Fu Lee, Cheng-Han Lu, Cheng-En Lee, Haruki Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan-Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang:
A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications. VLSI Technology and Circuits 2022: 24-25 - 2021
- [c8]Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo
An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. ISSCC 2021: 252-254
2000 – 2009
- 2001
- [c7]I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong
Integrated power supply planning and floorplanning. ASP-DAC 2001: 589-594 - 2000
- [j5]Hendrawan Soeleman, Kaushik Roy, Tan-Li Chou:
Estimating Circuit Activity in Combinational CMOS Digital Circuits. IEEE Des. Test Comput. 17(2): 112-119 (2000) - [c6]I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. ISPD 2000: 33-38
1990 – 1999
- 1998
- [j4]Tan-Li Chou, Kaushik Roy:
Power Estimation Under Uncertain Delays. Integr. Comput. Aided Eng. 5(2): 107-116 (1998) - [j3]Zhanping Chen, Kaushik Roy, Tan-Li Chou:
Efficient statistical approach to estimate power considering uncertain properties of primary inputs. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 484-492 (1998) - 1997
- [c5]Zhanping Chen, Kaushik Roy, Tan-Li Chou:
Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. ICCAD 1997: 40-44 - [c4]Priya Patil, Tan-Li Chou, Kaushik Roy, Rabindra Roy:
Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique. VLSI Design 1997: 179-184 - 1996
- [j2]Tan-Li Chou, Kaushik Roy:
Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1257-1265 (1996) - [j1]Tan-Li Chou, Kaushik Roy:
Accurate power estimation of CMOS sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 4(3): 369-380 (1996) - 1995
- [c3]Tan-Li Chou, Kaushik Roy:
Statistical estimation of sequential circuit activity. ICCAD 1995: 34-37 - [c2]Tan-Li Chou, Kaushik Roy:
Estimation of sequential circuit activity considering spatial and temporal correlations. ICCD 1995: 577-582 - 1994
- [c1]Tan-Li Chou, Kaushik Roy, Sharat Prasad:
Estimation of circuit activity considering signal correlations and simultaneous switching. ICCAD 1994: 300-303
Coauthor Index
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