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28th SBCCI 2015: Salvador, Brazil
- Robson Nunes de Lima, Ana Isabela Araújo Cunha, Calvin Plett, Wagner Luiz Alves de Oliveira:
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, SBCCI 2015, Salvador, Brazil, August 31 - September 4, 2015. ACM 2015, ISBN 978-1-4503-3763-2
Digital, Reconfigurable and Applications
- Andre Luis Rodeghiero Rosa, Leonardo Bandeira Soares, Kleber Hugo Stangherlin, Sergio Bampi
:
Designing CMOS for Near-Threshold Minimum-Energy Operation and Extremely Wide V-F Scaling. 1:1-1:6 - Ricardo A. Guazzelli, Fernando Gehm Moraes
SDDS-NCL Design: Analysis of Supply Voltage Scaling. 2:1-2:7 - Bruno Canal, Cicero S. Nunes, Renato P. Ribas, Eric E. Fabris:
MCML Gate Design for Standard Cell Library. 3:1-3:6 - Tiago S. Curtinhas, Tassio Cortes Cavalcante
Minimization and Encoding of High Performance Asynchronous State Machines Based on Genetic Algorithm. 4:1-4:6 - Michael Dreschmann, Jan Heisswolf, Michael Geiger, Manuel Haußecker, Jürgen Becker
A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers. 5:1-5:6
Analog & RF & Mixed Signal
- Jhon A. Gomez C.
High PSRR Nano-Watt MOS-Only Threshold Voltage Monitor Circuit. 6:1-6:6 - Sara Pashmineh, Dirk Killat:
Design of High-Voltage Level Shifters Based on Stacked Standard Transistors for a Wide Range of Supply Voltages. 7:1-7:6 - Renato Campana V.
0.5 V Supply Resistorless Voltage Reference for Low Voltage Applications. 8:1-8:6 - David Cordova, Pedro Toledo, Hamilton Klimach, Sergio Bampi
0.5 V Supply Voltage Reference Based on the MOSFET ZTC Condition. 9:1-9:7
SoC, NoC, Embedded
- Marcel Moscarelli Corrêa, Marcelo Schiavon Porto, Bruno Zatt, Luciano Volcan Agostini
A Low-Area and High-Throughput Intra Prediction Architecture for a Multi-Standard HEVC and H.264/AVC Video Encoder. 10:1-10:6 - Vladimir Afonso, Henrique Maich, Luan Audibert, Bruno Zatt, Marcelo Schiavon Porto, Luciano Volcan Agostini
Memory-Aware and High-Throughput Hardware Design for the HEVC Fractional Motion Estimation. 11:1-11:6 - Wagner Penny
Real-Time Architecture for HEVC Motion Compensation Sample Interpolator for UHD Videos. 12:1-12:6 - Marcelo Mandelli, Guilherme M. Castilhos, Gilles Sassatelli, Luciano Ost
A Distributed Energy-aware Task Mapping to Achieve Thermal Balancing and Improve Reliability of Many-core Systems. 13:1-13:7
CAD, Verification & Test
- Nico Hellwege, Nils Heidmann, Steffen Paul
Optimum Operating Points of Transistors with minimal Aging-Aware Sensitivity. 14:1-14:7 - Dayane Alfenas Reis
A novel methodology for robustness analysis of QCA circuits. 15:1-15:7 - Maicon Schneider Cardoso, Leomar Soares da Rosa Jr., Felipe de Souza Marques:
Evaluating Geometric Aspects of Non-Series-Parallel Cells. 16:1-16:6 - André B. M. Gomes, Fredy A. M. Alves, Ricardo S. Ferreira, José Augusto Miranda Nacif:
Increasing Observability in Post-Silicon Debug Using Asymmetric Omega Networks. 17:1-17:7 - Helder F. de A. Oliveira, Alisson Vasconcelos de Brito
Power-Aware Design of Electronic System Level using Interoperation of Hybrid and Distributed Simulations. 18:1-18:7 - Julia Casarin Puget, Guilherme Flach, Marcelo O. Johann, Ricardo Augusto da Luz Reis
Jezz: An Effective Legalization Algorithm for Minimum Displacement. 19:1-19:5 - Hiroyuki Yamauchi
A Phase Shifting Multiple Filter Design Methodology for Lucy-Richardson Deconvolution of Log-Mixtures Complex RTN Tail Distribution. 20:1-20:6
Analog & RF & Mixed Signal
- Pietro Maris Ferreira
Optimization Methodology for a 460-MHz-GBW and 80-dB-SNR Low-Power Current-Mode Amplifier. 21:1-21:6 - Rafael Cantalice, Alexandre Simionovski, Fernando Paixão Cortes, Marcelo Lubaszewski:
Low power, high-sensitivity clock recovery circuit for LF/HF RFID applications. 22:1-22:5 - Bernardo Leite
Design of 28 nm CMOS integrated transformers for a 60 GHz power amplifier. 23:1-23:6 - Linder Reyes, Fernando Silveira:
Analysis and Design of a MOS RF Envelope Detector in All Inversion Regions. 24:1-24:5 - Fabián Leonardo Cabrera
A 25-dBm 1-GHz Power Amplifier Integrated in CMOS 180nm for Wireless Power Transferring. 25:1-25:6
SoC, NoC, Embedded
- Johanna Sepúlveda, Daniel Flórez, Guy Gogniat
Reconfigurable Group-Wise Security Architecture for NoC-Based MPSoCs Protection. 26:1-26:6 - Jarbas Silveira
Smart Reconfiguration Approach for Fault-Tolerant NoC Based MPSoCs. 27:1-27:6 - Cezar R. W. Reinbrecht, Martha Johanna Sepúlveda, Altamiro Amadeu Susin:
PHiCIT: Improving Hierarchical Networks-on-chip through 3D Silicon Photonics Integration. 28:1-28:7 - Anelise Kologeski, Henrique Colao Zanuz, Fernanda Lima Kastensmidt
Latency Improvement with Traffic Flow Analysis in a 3D NoC under Multiple Faulty TSVs Scenario. 29:1-29:6
Analog & RF & Mixed Signal
- Filipe D. Baumgratz, Hao Li, Sergio Bampi
Wideband Low Noise Variable Gain Amplifier. 30:1-30:6 - Arthur Liraneto Torres Costa, Hamilton Klimach, Sergio Bampi
A 2-decades Wideband Low-Noise Amplifier with High Gain and ESD Protection. 31:1-31:6 - Pedro Toledo, Hamilton Klimach, David Cordova, Sergio Bampi
CMOS Transconductor Analysis for Low Temperature Sensitivity Based on ZTC MOSFET Condition. 32:1-32:7 - André F. Ponchet, Ezio M. Bastida, Roberto R. Panepucci
Design and Optimization of High Sensitivity Transimpedance Amplifiers in 130 nm CMOS and BiCMOS Technologies for High Speed Optical Receivers. 33:1-33:6 - Raphael Andreoni Camponogara Viera
System-level Design of Single-bit Sigma-Delta Modulators Based on MSA and SNR Data Graphics. 34:1-34:6 - Lucas Teixeira
Direct Feedback Topology for Reducing Residual Voltage in Functional Electrical Stimulation. 35:1-35:4 - Antonio Wallace Antunes Soares, Diomadson R. Belfort, Sebastian Yuri Cavalcanti Catunda
Analysis and System-Level Design of a High Resolution Incremental ΣΔ ADC for Biomedical Applications. 36:1-36:6 - Raafat Lababidi, Frédéric Le Roy, D. Le Jeune, Ali Mansour, Julien Lintignat, Ali Louzir:
Highly integrated Active Dual Response Filter. 37:1-37:4 - Ewerton Gomes de Oliveira
Effective Cross Comparison of Mismatch Effects on Different Logarithmic Pixel Sensor Topologies. 38:1-38:2
Digital, Reconfigurable and Applications
- Abel G. Silva-Filho, L. J. C. Nunes, Henrique F. Lacerda:
Differential Evolution to Reduce Energy Consumption in Three-Level Memory Hierarchy. 39:1-39:6 - Thiago R. B. S. Soares, Ivan Saraiva Silva, Sílvio R. F. de Fernandes:
IPNoSys II: A New Architecture for IPNoSys Programming Model. 40:1-40:7 - Jefferson Capovilla, Mario Lúcio Côrtes, Guido Araujo:
Improving the Statistical Variability of Delay-based Physical Unclonable Functions. 41:1-41:7 - Bruno A. Silva, Lucas Albers Cuminato, Vanderlei Bonato
Run-time Cache Configuration for the LEON-3 Embedded Processor. 42:1-42:6 - Jader A. De Lima, Wallace A. Pimenta:
A Current Limiter for Linear Regulators Based on Power-Dissipation Threshold. 43:1-43:5
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